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treewide: Bump AXI-RT and fix AXI-RT functional tests #118
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Bender: Bump `axi_rt` AXI real-time unit
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Bender: Bump AXI-REALM
Bender: Bump AXI-REALM and fix AXI-REALM functional tests
Oct 22, 2024
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I can't speak on the tests, it's best to talk that over with @thommythomaso.
The nonfree change is fine and has been merged.
I just have one small comment below.
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* Fix functional bug
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This parameter in the makefrag affects the number of registers generated inside the AXI-REALM IP. The default value, associated with the default configuration of Cheshire, is 6, accounting for: `core0`, `debug module`, `dma`, `serial link`, `vga` and `usb`. Change accordingly if the configuration changes, e.g., the number of cores or if new managers are added.
Add utility function to get the manager id of cheshire according to the implemented HW features, thus removing any hardcoded parametrization (the number of application-class cores, as well as the specific hardware features, are configurable, hence not known a priori)
* Fix check on budget left for W and R transactions
Test that the manager is isolated when the transfer size exceeds the available budget
* Add AXI-REALM isolation test to CI
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Bender: Bump AXI-REALM and fix AXI-REALM functional tests
treewide: Bump AXI-RT and fix AXI-RT functional tests
Nov 28, 2024
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Bump AXI-REALM to latest version. Fixes functional bug in the write buffer module (Various fixes and improvements axi_rt#11).
Fix default number of configuration registers in
cheshire.mk
Fix budget (W/R) left check in
axirt_budget.c
testAdd
axirt_budget_isolation.c
test to check manager isolation through AXI-REALM after budget expires (transfer size > budget)Further additions:
tclint
version to 0.4.2CHSROOT
to staticrealpath
(pwd
may not be a fully qualified path)helloworld
tests