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what happens for combinational loops through a register's async reset input?
#260
opened Dec 2, 2024 by
programmerjake
what is an enum's corresponding mask type? for memory write ports
#211
opened May 13, 2024 by
programmerjake
Ability to reference and generate modules with escaped identifiers?
#134
opened Oct 18, 2023 by
smarter
Should the File Preamble be enhanced to include the ABI version?
#132
opened Oct 18, 2023 by
smarter
Determine how to handle non-Verilog legal Extmodule DefName, i.e., Literal Identifiers
#115
opened Jun 21, 2023 by
seldridge
[abi] Add rules / hints / conventions for how names are lowered to SystemVerilog
#113
opened May 25, 2023 by
mmaloney-sf
FIRRTL Rationale
documentation
Improvements or additions to documentation
enhancement
New feature or request
#85
opened Mar 7, 2023 by
dtzSiFive
ProTip!
Follow long discussions with comments:>50.