vectorize slice::is_sorted

[LaihoE]

Benchmarks using u32 slices:

len	New	Old
2	1.1997 ns	889.23 ps
4	1.6479 ns	1.5396 ns
8	2.5764 ns	2.5633 ns
16	5.4750 ns	4.7421 ns
32	11.344 ns	8.4634 ns
64	12.105 ns	18.104 ns
128	17.263 ns	33.185 ns
256	29.465 ns	60.928 ns
512	48.926 ns	116.19 ns
1024	85.274 ns	237.91 ns
2048	160.94 ns	469.53 ns
4096	311.60 ns	911.43 ns
8192	615.89 ns	2.2316 µs
16384	1.2619 µs	3.4871 µs
32768	2.5245 µs	6.9947 µs
65536	5.2254 µs	15.212 µs

Seems to be a bit slower on small N but much faster on large N.

Godbolt: https://rust.godbolt.org/z/Txn5MdfKn

[rustbot]

r? @thomcc

rustbot has assigned @thomcc.
They will have a look at your PR within the next two weeks and either review your PR or reassign to another reviewer.

Use r? to explicitly pick a reviewer

[clubby789]

Not seeing many uses of this in rustc itself but worth checking:
@bors try @rust-timer queue

[bors]

⌛ Trying commit 3855cb8 with merge d8d4110...

[bors]

☀️ Try build successful - checks-actions
Build commit: d8d4110 (d8d4110c5e02792f11d378b725b30c28ae0908c9)

[rust-timer]

Finished benchmarking commit (d8d4110): comparison URL.

Overall result: ✅ improvements - no action needed

Benchmarking this pull request likely means that it is perf-sensitive, so we're automatically marking it as not fit for rolling up. While you can manually mark this PR as fit for rollup, we strongly recommend not doing so since this PR may lead to changes in compiler perf.

@bors rollup=never
@rustbot label: -S-waiting-on-perf -perf-regression

Instruction count

This is the most reliable metric that we have; it was used to determine the overall result at the top of this comment. However, even this metric can sometimes exhibit noise.

	mean	range	count
Regressions ❌ (primary)	-	-	0
Regressions ❌ (secondary)	-	-	0
Improvements ✅ (primary)	-	-	0
Improvements ✅ (secondary)	-0.5%	[-0.5%, -0.4%]	2
All ❌✅ (primary)	-	-	0

Max RSS (memory usage)

Results (primary -1.8%)

This is a less reliable metric that may be of interest but was not used to determine the overall result at the top of this comment.

	mean	range	count
Regressions ❌ (primary)	-	-	0
Regressions ❌ (secondary)	-	-	0
Improvements ✅ (primary)	-1.8%	[-1.8%, -1.8%]	1
Improvements ✅ (secondary)	-	-	0
All ❌✅ (primary)	-1.8%	[-1.8%, -1.8%]	1

Cycles

Results (secondary -2.1%)

This is a less reliable metric that may be of interest but was not used to determine the overall result at the top of this comment.

	mean	range	count
Regressions ❌ (primary)	-	-	0
Regressions ❌ (secondary)	-	-	0
Improvements ✅ (primary)	-	-	0
Improvements ✅ (secondary)	-2.1%	[-2.2%, -2.0%]	4
All ❌✅ (primary)	-	-	0

Binary size

This benchmark run did not return any relevant results for this metric.

Bootstrap: 786.53s -> 786.425s (-0.01%)
Artifact size: 335.31 MiB -> 335.34 MiB (0.01%)

[Kobzol]

FWIW, the two changed benchmarks are most likely spurious, they are oscillating currently. So it's perf. neutral on compiler benchmarks, which is fine.

[thomcc]

Seems fine to me.

@bors r+

[bors]

📌 Commit 3855cb8 has been approved by thomcc

It is now in the queue for this repository.

[bors]

⌛ Testing commit 3855cb8 with merge 44f233f...

[bors]

☀️ Test successful - checks-actions
Approved by: thomcc
Pushing 44f233f to master...

[rust-timer]

Finished benchmarking commit (44f233f): comparison URL.

Overall result: ❌ regressions - no action needed

@rustbot label: -perf-regression

Instruction count

This is the most reliable metric that we have; it was used to determine the overall result at the top of this comment. However, even this metric can sometimes exhibit noise.

	mean	range	count
Regressions ❌ (primary)	-	-	0
Regressions ❌ (secondary)	0.3%	[0.3%, 0.3%]	2
Improvements ✅ (primary)	-	-	0
Improvements ✅ (secondary)	-	-	0
All ❌✅ (primary)	-	-	0

Max RSS (memory usage)

Results (primary -1.7%, secondary -1.6%)

This is a less reliable metric that may be of interest but was not used to determine the overall result at the top of this comment.

	mean	range	count
Regressions ❌ (primary)	-	-	0
Regressions ❌ (secondary)	-	-	0
Improvements ✅ (primary)	-1.7%	[-1.7%, -1.7%]	1
Improvements ✅ (secondary)	-1.6%	[-1.7%, -1.5%]	3
All ❌✅ (primary)	-1.7%	[-1.7%, -1.7%]	1

Cycles

Results (secondary 2.1%)

This is a less reliable metric that may be of interest but was not used to determine the overall result at the top of this comment.

	mean	range	count
Regressions ❌ (primary)	-	-	0
Regressions ❌ (secondary)	2.1%	[1.9%, 2.3%]	3
Improvements ✅ (primary)	-	-	0
Improvements ✅ (secondary)	-	-	0
All ❌✅ (primary)	-	-	0

Binary size

This benchmark run did not return any relevant results for this metric.

Bootstrap: 785.272s -> 784.378s (-0.11%)
Artifact size: 335.35 MiB -> 335.40 MiB (0.02%)

[therealprof]

It would be nice if we could check impacts not only on x86_64 but also (at least) on aarch64. The original function was already partially vectorized on x86_64 but the new generated code is growing substantially on ARMv7 and to a lesser extent on aarch64 and I do have doubts about this being a universal improvement...

[LaihoE]

I'm completely fine with reverting this if there are concerns with other targets. The improvements on x86 are not that big.

The original function was already partially vectorized on x86_64

Do you have an example of this? I would expect that optimization to be illegal as the old function used all() that short circuits on every element.

I must admit that my experience with aarch64 is quite limited but isn't this a fine hot loop?

.LBB0_4:
        ldp     q1, q2, [x10, #-32]
        ldur    q3, [x10, #-28]
        ldur    q4, [x10, #-12]
        ldur    q17, [x10, #-76]
        ldur    q18, [x10, #-60]
        ldur    q19, [x10, #-44]
        ldur    q20, [x10, #-124]
        ldur    q21, [x10, #-108]
        cmgt    v2.4s, v2.4s, v4.4s
        cmgt    v1.4s, v1.4s, v3.4s
        ldur    q22, [x10, #-92]
        ldp     q5, q6, [x10, #-128]
        ldp     q3, q4, [x10, #-96]
        uzp1    v1.8h, v1.8h, v2.8h
        ldp     q7, q16, [x10, #-64]
        cmgt    v6.4s, v6.4s, v21.4s
        cmgt    v5.4s, v5.4s, v20.4s
        cmgt    v4.4s, v4.4s, v17.4s
        cmgt    v3.4s, v3.4s, v22.4s
        cmgt    v16.4s, v16.4s, v19.4s
        cmgt    v7.4s, v7.4s, v18.4s
        uzp1    v3.8h, v3.8h, v4.8h
        uzp1    v4.8h, v5.8h, v6.8h
        uzp1    v2.8h, v7.8h, v16.8h
        uzp1    v1.16b, v2.16b, v1.16b
        uzp1    v2.16b, v4.16b, v3.16b
        and     v1.16b, v1.16b, v0.16b
        and     v2.16b, v2.16b, v0.16b
        ext     v3.16b, v1.16b, v1.16b, #8
        ext     v4.16b, v2.16b, v2.16b, #8
        zip1    v1.16b, v1.16b, v3.16b
        zip1    v2.16b, v2.16b, v4.16b
        addv    h1, v1.8h
        addv    h2, v2.8h
        fmov    w12, s1
        fmov    w13, s2
        orr     w12, w13, w12
        tst     w12, #0xffff
        b.ne    .LBB0_36
        add     x11, x11, #32
        add     x10, x10, #128
        cmp     x11, x9
        b.lo    .LBB0_4

generated code is growing substantially on ARMv7 and to a lesser extent on aarch64

How about setting the CHUNK_SIZE to 9?

[therealprof]

Do you have an example of this? I would expect that optimization to be illegal as the old function used all() that short circuits on every element.

Upon closer inspection it seems I've mistaken the (vectorized) initialisation for the is_sorted implementation.

However I did a few more generated code comparisons (excluding the lookup tables). And what is even worse: the vectorisation only works on opt-level 3, in other opt-levels the number of insns (haven't dared to check actual code size) is
significantly larger than the vectorised code and most likely also a lot slower, both on x864_64 and aarch64.

On x86_64 (opt-level 3):

        push    rax
        cmp     rsi, 32
        ja      .LBB0_4
        add     rdi, 4
.LBB0_2:
        cmp     rsi, 2
        setb    al
        jb      .LBB0_14
        dec     rsi
        mov     ecx, dword ptr [rdi - 4]
        lea     rdx, [rdi + 4]
        cmp     ecx, dword ptr [rdi]
        mov     rdi, rdx
        jbe     .LBB0_2
.LBB0_14:
        pop     rcx
        ret
.LBB0_4:
        mov     rcx, rsi
        xor     eax, eax
        add     rcx, -33
        je      .LBB0_5
        movdqa  xmm0, xmmword ptr [rip + .LCPI0_0]
.LBB0_12:
        movdqu  xmm1, xmmword ptr [rdi + 4*rax + 48]
        movdqu  xmm3, xmmword ptr [rdi + 4*rax + 80]
        movdqu  xmm4, xmmword ptr [rdi + 4*rax + 64]
        movdqu  xmm2, xmmword ptr [rdi + 4*rax]
        movdqu  xmm5, xmmword ptr [rdi + 4*rax + 68]
        pxor    xmm5, xmm0
        pxor    xmm4, xmm0
        pcmpgtd xmm4, xmm5
        movdqu  xmm5, xmmword ptr [rdi + 4*rax + 4]
        pxor    xmm5, xmm0
        pxor    xmm2, xmm0
        pcmpgtd xmm2, xmm5
        movdqu  xmm5, xmmword ptr [rdi + 4*rax + 84]
        por     xmm2, xmm4
        movdqu  xmm6, xmmword ptr [rdi + 4*rax + 16]
        pxor    xmm5, xmm0
        pxor    xmm3, xmm0
        pcmpgtd xmm3, xmm5
        movdqu  xmm4, xmmword ptr [rdi + 4*rax + 20]
        pxor    xmm4, xmm0
        pxor    xmm6, xmm0
        pcmpgtd xmm6, xmm4
        movdqu  xmm4, xmmword ptr [rdi + 4*rax + 32]
        por     xmm6, xmm3
        movdqu  xmm3, xmmword ptr [rdi + 4*rax + 96]
        packssdw        xmm2, xmm6
        movdqu  xmm5, xmmword ptr [rdi + 4*rax + 100]
        pxor    xmm5, xmm0
        pxor    xmm3, xmm0
        pcmpgtd xmm3, xmm5
        movdqu  xmm5, xmmword ptr [rdi + 4*rax + 36]
        pxor    xmm5, xmm0
        pxor    xmm4, xmm0
        pcmpgtd xmm4, xmm5
        movdqu  xmm5, xmmword ptr [rdi + 4*rax + 112]
        por     xmm4, xmm3
        movdqu  xmm3, xmmword ptr [rdi + 4*rax + 116]
        pxor    xmm3, xmm0
        pxor    xmm5, xmm0
        pcmpgtd xmm5, xmm3
        movdqu  xmm3, xmmword ptr [rdi + 4*rax + 52]
        pxor    xmm3, xmm0
        pxor    xmm1, xmm0
        pcmpgtd xmm1, xmm3
        por     xmm1, xmm5
        packssdw        xmm4, xmm1
        packsswb        xmm2, xmm4
        pmovmskb        edx, xmm2
        test    edx, edx
        jne     .LBB0_13
        add     rax, 32
        cmp     rax, rcx
        jb      .LBB0_12
        cmp     rax, rsi
        ja      .LBB0_10
.LBB0_5:
        sub     rsi, rax
        lea     rcx, [rdi + 4*rax]
        add     rcx, 4
.LBB0_6:
        cmp     rsi, 2
        setb    al
        jb      .LBB0_14
        dec     rsi
        mov     edx, dword ptr [rcx - 4]
        lea     rdi, [rcx + 4]
        cmp     edx, dword ptr [rcx]
        mov     rcx, rdi
        jbe     .LBB0_6
        jmp     .LBB0_14
.LBB0_13:
        xor     eax, eax
        pop     rcx
        ret
.LBB0_10:
        lea     rdx, [rip + .L__unnamed_1]
        mov     rdi, rax
        call    qword ptr [rip + core::slice::index::slice_start_index_len_fail::h818a98ee9244191a@GOTPCREL]

On x86_64 (opt-level 2):

        push    rax
        cmp     rsi, 32
        ja      .LBB0_4
        add     rdi, 4
.LBB0_2:
        cmp     rsi, 2
        setb    al
        jb      .LBB0_8
        dec     rsi
        mov     ecx, dword ptr [rdi - 4]
        lea     rdx, [rdi + 4]
        cmp     ecx, dword ptr [rdi]
        mov     rdi, rdx
        jbe     .LBB0_2
        jmp     .LBB0_8
.LBB0_4:
        mov     rdx, rsi
        xor     ecx, ecx
        add     rdx, -33
        je      .LBB0_5
        xor     eax, eax
.LBB0_12:
        mov     r8d, dword ptr [rdi + 4*rcx + 4]
        cmp     dword ptr [rdi + 4*rcx], r8d
        ja      .LBB0_8
        mov     r9d, dword ptr [rdi + 4*rcx + 8]
        cmp     r8d, r9d
        ja      .LBB0_8
        mov     r8d, dword ptr [rdi + 4*rcx + 12]
        cmp     r9d, r8d
        ja      .LBB0_8
        mov     r9d, dword ptr [rdi + 4*rcx + 16]
        cmp     r8d, r9d
        ja      .LBB0_8
        mov     r8d, dword ptr [rdi + 4*rcx + 20]
        cmp     r9d, r8d
        ja      .LBB0_8
        mov     r9d, dword ptr [rdi + 4*rcx + 24]
        cmp     r8d, r9d
        ja      .LBB0_8
        mov     r8d, dword ptr [rdi + 4*rcx + 28]
        cmp     r9d, r8d
        ja      .LBB0_8
        mov     r9d, dword ptr [rdi + 4*rcx + 32]
        cmp     r8d, r9d
        ja      .LBB0_8
        mov     r8d, dword ptr [rdi + 4*rcx + 36]
        cmp     r9d, r8d
        ja      .LBB0_8
        mov     r9d, dword ptr [rdi + 4*rcx + 40]
        cmp     r8d, r9d
        ja      .LBB0_8
        mov     r8d, dword ptr [rdi + 4*rcx + 44]
        cmp     r9d, r8d
        ja      .LBB0_8
        mov     r9d, dword ptr [rdi + 4*rcx + 48]
        cmp     r8d, r9d
        ja      .LBB0_8
        mov     r8d, dword ptr [rdi + 4*rcx + 52]
        cmp     r9d, r8d
        ja      .LBB0_8
        mov     r9d, dword ptr [rdi + 4*rcx + 56]
        cmp     r8d, r9d
        ja      .LBB0_8
        mov     r8d, dword ptr [rdi + 4*rcx + 60]
        cmp     r9d, r8d
        ja      .LBB0_8
        mov     r9d, dword ptr [rdi + 4*rcx + 64]
        cmp     r8d, r9d
        ja      .LBB0_8
        mov     r8d, dword ptr [rdi + 4*rcx + 68]
        cmp     r9d, r8d
        ja      .LBB0_8
        mov     r9d, dword ptr [rdi + 4*rcx + 72]
        cmp     r8d, r9d
        ja      .LBB0_8
        mov     r8d, dword ptr [rdi + 4*rcx + 76]
        cmp     r9d, r8d
        ja      .LBB0_8
        mov     r9d, dword ptr [rdi + 4*rcx + 80]
        cmp     r8d, r9d
        ja      .LBB0_8
        mov     r8d, dword ptr [rdi + 4*rcx + 84]
        cmp     r9d, r8d
        ja      .LBB0_8
        mov     r9d, dword ptr [rdi + 4*rcx + 88]
        cmp     r8d, r9d
        ja      .LBB0_8
        mov     r8d, dword ptr [rdi + 4*rcx + 92]
        cmp     r9d, r8d
        ja      .LBB0_8
        mov     r9d, dword ptr [rdi + 4*rcx + 96]
        cmp     r8d, r9d
        ja      .LBB0_8
        mov     r8d, dword ptr [rdi + 4*rcx + 100]
        cmp     r9d, r8d
        ja      .LBB0_8
        mov     r9d, dword ptr [rdi + 4*rcx + 104]
        cmp     r8d, r9d
        ja      .LBB0_8
        mov     r8d, dword ptr [rdi + 4*rcx + 108]
        cmp     r9d, r8d
        ja      .LBB0_8
        mov     r9d, dword ptr [rdi + 4*rcx + 112]
        cmp     r8d, r9d
        ja      .LBB0_8
        mov     r8d, dword ptr [rdi + 4*rcx + 116]
        cmp     r9d, r8d
        ja      .LBB0_8
        mov     r9d, dword ptr [rdi + 4*rcx + 120]
        cmp     r8d, r9d
        ja      .LBB0_8
        mov     r8d, dword ptr [rdi + 4*rcx + 124]
        cmp     r9d, r8d
        ja      .LBB0_8
        cmp     r8d, dword ptr [rdi + 4*rcx + 128]
        ja      .LBB0_8
        add     rcx, 32
        cmp     rcx, rdx
        jb      .LBB0_12
        cmp     rcx, rsi
        ja      .LBB0_10
.LBB0_5:
        sub     rsi, rcx
        lea     rcx, [rdi + 4*rcx]
        add     rcx, 4
.LBB0_6:
        cmp     rsi, 2
        setb    al
        jb      .LBB0_8
        dec     rsi
        mov     edx, dword ptr [rcx - 4]
        lea     rdi, [rcx + 4]
        cmp     edx, dword ptr [rcx]
        mov     rcx, rdi
        jbe     .LBB0_6
.LBB0_8:
        pop     rcx
        ret
.LBB0_10:
        lea     rdx, [rip + .L__unnamed_1]
        mov     rdi, rcx
        call    qword ptr [rip + core::slice::index::slice_start_index_len_fail::h818a98ee9244191a@GOTPCREL]

vs (old):

        xor     eax, eax
        sub     rsi, 1
        cmovb   rsi, rax
.LBB0_1:
        mov     rcx, rax
        cmp     rsi, rax
        je      .LBB0_3
        mov     edx, dword ptr [rdi + 4*rcx]
        lea     rax, [rcx + 1]
        cmp     edx, dword ptr [rdi + 4*rcx + 4]
        jbe     .LBB0_1
.LBB0_3:
        cmp     rsi, rcx
        sete    al
        ret

On aarch64 (opt-level 3):

        sub     sp, sp, #32
        stp     x29, x30, [sp, #16]
        add     x29, sp, #16
        cmp     x1, #32
        b.hi    LBB0_4
        add     x8, x0, #4
LBB0_2:
        cmp     x1, #2
        cset    w0, lo
        b.lo    LBB0_13
        sub     x1, x1, #1
        ldp     w9, w10, [x8, #-4]
        add     x8, x8, #4
        cmp     w9, w10
        b.ls    LBB0_2
        b       LBB0_13
LBB0_4:
        mov     x8, #0
        subs    x9, x1, #33
        b.eq    LBB0_9
        add     x10, x0, #128
        adrp    x11, lCPI0_0@PAGE
        ldr     q0, [x11, lCPI0_0@PAGEOFF]
LBB0_6:
        ldp     q1, q2, [x10, #-128]
        ldp     q3, q4, [x10, #-96]
        ldp     q5, q6, [x10, #-64]
        ldp     q7, q16, [x10, #-32]
        ldur    q17, [x10, #-124]
        ldur    q18, [x10, #-108]
        ldur    q19, [x10, #-92]
        ldur    q20, [x10, #-76]
        ldur    q21, [x10, #-60]
        ldur    q22, [x10, #-44]
        ldur    q23, [x10, #-28]
        ldur    q24, [x10, #-12]
        cmhi.4s v16, v16, v24
        cmhi.4s v7, v7, v23
        uzp1.8h v7, v7, v16
        cmhi.4s v6, v6, v22
        cmhi.4s v5, v5, v21
        uzp1.8h v5, v5, v6
        uzp1.16b        v5, v5, v7
        and.16b v5, v5, v0
        ext.16b v6, v5, v5, #8
        zip1.16b        v5, v5, v6
        addv.8h h5, v5
        fmov    w11, s5
        cmhi.4s v4, v4, v20
        cmhi.4s v3, v3, v19
        uzp1.8h v3, v3, v4
        cmhi.4s v2, v2, v18
        cmhi.4s v1, v1, v17
        uzp1.8h v1, v1, v2
        uzp1.16b        v1, v1, v3
        and.16b v1, v1, v0
        ext.16b v2, v1, v1, #8
        zip1.16b        v1, v1, v2
        addv.8h h1, v1
        fmov    w12, s1
        orr     w11, w12, w11
        tst     w11, #0xffff
        b.ne    LBB0_12
        add     x8, x8, #32
        add     x10, x10, #128
        cmp     x8, x9
        b.lo    LBB0_6
        cmp     x8, x1
        b.hi    LBB0_14
LBB0_9:
        sub     x9, x1, x8
        add     x8, x0, x8, lsl #2
        add     x8, x8, #4
LBB0_10:
        cmp     x9, #2
        cset    w0, lo
        b.lo    LBB0_13
        sub     x9, x9, #1
        ldp     w10, w11, [x8, #-4]
        add     x8, x8, #4
        cmp     w10, w11
        b.ls    LBB0_10
        b       LBB0_13
LBB0_12:
        mov     w0, #0
LBB0_13:
        ldp     x29, x30, [sp, #16]
        add     sp, sp, #32
        ret
LBB0_14:
        adrp    x2, l___unnamed_1@PAGE
        add     x2, x2, l___unnamed_1@PAGEOFF
        mov     x0, x8
        bl      __ZN4core5slice5index26slice_start_index_len_fail17h8e009aba8a824b46E

vs. aarch64 (opt-level 2):

        stp     x29, x30, [sp, #-16]!
        mov     x29, sp
        cmp     x1, #32
        b.hi    LBB0_4
        add     x8, x0, #4
LBB0_2:
        cmp     x1, #2
        cset    w0, lo
        b.lo    LBB0_44
        sub     x1, x1, #1
        ldp     w9, w10, [x8, #-4]
        add     x8, x8, #4
        cmp     w9, w10
        b.ls    LBB0_2
        b       LBB0_44
LBB0_4:
        mov     x8, #0
        subs    x10, x1, #33
        b.eq    LBB0_41
        mov     x9, x0
        add     x11, x0, #64
LBB0_6:
        mov     w0, #0
        ldp     w13, w12, [x11, #-64]
        cmp     w13, w12
        b.hi    LBB0_44
        ldur    w13, [x11, #-56]
        cmp     w12, w13
        b.hi    LBB0_44
        ldur    w12, [x11, #-52]
        cmp     w13, w12
        b.hi    LBB0_44
        ldur    w13, [x11, #-48]
        cmp     w12, w13
        b.hi    LBB0_44
        ldur    w12, [x11, #-44]
        cmp     w13, w12
        b.hi    LBB0_44
        ldur    w13, [x11, #-40]
        cmp     w12, w13
        b.hi    LBB0_44
        ldur    w12, [x11, #-36]
        cmp     w13, w12
        b.hi    LBB0_44
        ldur    w13, [x11, #-32]
        cmp     w12, w13
        b.hi    LBB0_44
        ldur    w12, [x11, #-28]
        cmp     w13, w12
        b.hi    LBB0_44
        ldur    w13, [x11, #-24]
        cmp     w12, w13
        b.hi    LBB0_44
        ldur    w12, [x11, #-20]
        cmp     w13, w12
        b.hi    LBB0_44
        ldur    w13, [x11, #-16]
        cmp     w12, w13
        b.hi    LBB0_44
        ldur    w12, [x11, #-12]
        cmp     w13, w12
        b.hi    LBB0_44
        ldur    w13, [x11, #-8]
        cmp     w12, w13
        b.hi    LBB0_44
        ldur    w12, [x11, #-4]
        cmp     w13, w12
        b.hi    LBB0_44
        ldr     w13, [x11]
        cmp     w12, w13
        b.hi    LBB0_44
        ldr     w12, [x11, #4]
        cmp     w13, w12
        b.hi    LBB0_44
        ldr     w13, [x11, #8]
        cmp     w12, w13
        b.hi    LBB0_44
        ldr     w12, [x11, #12]
        cmp     w13, w12
        b.hi    LBB0_44
        ldr     w13, [x11, #16]
        cmp     w12, w13
        b.hi    LBB0_44
        ldr     w12, [x11, #20]
        cmp     w13, w12
        b.hi    LBB0_44
        ldr     w13, [x11, #24]
        cmp     w12, w13
        b.hi    LBB0_44
        ldr     w12, [x11, #28]
        cmp     w13, w12
        b.hi    LBB0_44
        ldr     w13, [x11, #32]
        cmp     w12, w13
        b.hi    LBB0_44
        ldr     w12, [x11, #36]
        cmp     w13, w12
        b.hi    LBB0_44
        ldr     w13, [x11, #40]
        cmp     w12, w13
        b.hi    LBB0_44
        ldr     w12, [x11, #44]
        cmp     w13, w12
        b.hi    LBB0_44
        ldr     w13, [x11, #48]
        cmp     w12, w13
        b.hi    LBB0_44
        ldr     w12, [x11, #52]
        cmp     w13, w12
        b.hi    LBB0_44
        ldr     w13, [x11, #56]
        cmp     w12, w13
        b.hi    LBB0_44
        ldr     w12, [x11, #60]
        cmp     w13, w12
        b.hi    LBB0_44
        ldr     w13, [x11, #64]
        cmp     w12, w13
        b.hi    LBB0_44
        add     x11, x11, #128
        add     x8, x8, #32
        cmp     x8, x10
        b.lo    LBB0_6
        cmp     x8, x1
        b.hi    LBB0_45
        mov     x0, x9
LBB0_41:
        sub     x9, x1, x8
        add     x8, x0, x8, lsl #2
        add     x8, x8, #4
LBB0_42:
        cmp     x9, #2
        cset    w0, lo
        b.lo    LBB0_44
        sub     x9, x9, #1
        ldp     w10, w11, [x8, #-4]
        add     x8, x8, #4
        cmp     w10, w11
        b.ls    LBB0_42
LBB0_44:
        ldp     x29, x30, [sp], #16
        ret
LBB0_45:
        adrp    x2, l___unnamed_1@PAGE
        add     x2, x2, l___unnamed_1@PAGEOFF
        mov     x0, x8
        bl      __ZN4core5slice5index26slice_start_index_len_fail17h8e009aba8a824b46E

vs. (old):

        add     x8, x0, #4
        cmp     x1, #1
        csinc   x9, x1, xzr, lo
        sub     x10, x9, x1
LBB0_1:
        mov     x9, x10
        cbz     x10, LBB0_3
        ldp     w11, w12, [x8, #-4]
        add     x8, x8, #4
        add     x10, x9, #1
        cmp     w11, w12
        b.ls    LBB0_1
LBB0_3:
        cmp     x9, #0
        cset    w0, eq
        ret

It gets worse from there, on armv7 (both opt-level 2 and 3):

        push    {r4, r5, r6, lr}
        mov     lr, r0
        cmp     r1, #32
        bhi     .LBB0_4
        add     r2, lr, #4
.LBB0_2:
        cmp     r1, #2
        mov     r0, #0
        movwlo  r0, #1
        blo     .LBB0_27
        add     r3, r2, #4
        ldr     r5, [r2]
        ldr     r2, [r2, #-4]
        sub     r1, r1, #1
        cmp     r2, r5
        mov     r2, r3
        bls     .LBB0_2
        b       .LBB0_27
.LBB0_4:
        subs    r12, r1, #33
        mov     r3, #0
        beq     .LBB0_24
        add     r2, lr, #128
        mov     r0, #0
.LBB0_6:
        add     r4, lr, r3, lsl #2
        ldr     r6, [r2, #-128]
        ldr     r5, [r4, #4]
        cmp     r6, r5
        ldrls   r6, [r4, #8]
        cmpls   r5, r6
        bhi     .LBB0_27
        ldr     r5, [r4, #12]
        cmp     r6, r5
        ldrls   r6, [r4, #16]
        cmpls   r5, r6
        bhi     .LBB0_27
        ldr     r5, [r4, #20]
        cmp     r6, r5
        ldrls   r6, [r4, #24]
        cmpls   r5, r6
        bhi     .LBB0_27
        ldr     r5, [r4, #28]
        cmp     r6, r5
        ldrls   r6, [r4, #32]
        cmpls   r5, r6
        bhi     .LBB0_27
        ldr     r5, [r4, #36]
        cmp     r6, r5
        ldrls   r6, [r4, #40]
        cmpls   r5, r6
        bhi     .LBB0_27
        ldr     r5, [r4, #44]
        cmp     r6, r5
        ldrls   r6, [r4, #48]
        cmpls   r5, r6
        bhi     .LBB0_27
        ldr     r5, [r4, #52]
        cmp     r6, r5
        ldrls   r6, [r4, #56]
        cmpls   r5, r6
        bhi     .LBB0_27
        ldr     r5, [r4, #60]
        cmp     r6, r5
        ldrls   r6, [r4, #64]
        cmpls   r5, r6
        bhi     .LBB0_27
        ldr     r5, [r4, #68]
        cmp     r6, r5
        ldrls   r6, [r4, #72]
        cmpls   r5, r6
        bhi     .LBB0_27
        ldr     r5, [r4, #76]
        cmp     r6, r5
        ldrls   r6, [r4, #80]
        cmpls   r5, r6
        bhi     .LBB0_27
        ldr     r5, [r4, #84]
        cmp     r6, r5
        ldrls   r6, [r4, #88]
        cmpls   r5, r6
        bhi     .LBB0_27
        ldr     r5, [r4, #92]
        cmp     r6, r5
        ldrls   r6, [r4, #96]
        cmpls   r5, r6
        bhi     .LBB0_27
        ldr     r5, [r4, #100]
        cmp     r6, r5
        ldrls   r6, [r4, #104]
        cmpls   r5, r6
        bhi     .LBB0_27
        ldr     r5, [r4, #108]
        cmp     r6, r5
        ldrls   r6, [r4, #112]
        cmpls   r5, r6
        bhi     .LBB0_27
        ldr     r5, [r4, #116]
        cmp     r6, r5
        ldrls   r6, [r4, #120]
        cmpls   r5, r6
        bhi     .LBB0_27
        ldr     r4, [r4, #124]
        cmp     r6, r4
        ldrls   r5, [r2]
        cmpls   r4, r5
        bhi     .LBB0_27
        add     r3, r3, #32
        add     r2, r2, #128
        cmp     r3, r12
        blo     .LBB0_6
        cmp     r3, r1
        bhi     .LBB0_28
.LBB0_24:
        add     r0, lr, r3, lsl #2
        sub     r1, r1, r3
        add     r2, r0, #4
.LBB0_25:
        cmp     r1, #2
        mov     r0, #0
        movwlo  r0, #1
        blo     .LBB0_27
        add     r3, r2, #4
        ldr     r5, [r2]
        ldr     r2, [r2, #-4]
        sub     r1, r1, #1
        cmp     r2, r5
        mov     r2, r3
        bls     .LBB0_25
.LBB0_27:
        pop     {r4, r5, r6, pc}
.LBB0_28:
        ldr     r2, .LCPI0_0
        mov     r0, r3
.LPC0_0:
        add     r2, pc, r2
        bl      core::slice::index::slice_start_index_len_fail::h3874335222775e64
.LCPI0_0:
        .long   .L__unnamed_1-(.LPC0_0+8)

vs.

        push    {r5, lr}
        cmp     r1, #1
        mov     r2, r1
        movhs   r2, #1
        add     r0, r0, #4
        sub     r2, r2, r1
.LBB0_1:
        mov     r1, r2
        cmp     r2, #0
        beq     .LBB0_3
        add     r3, r0, #4
        ldr     r5, [r0]
        ldr     r0, [r0, #-4]
        add     r2, r1, #1
        cmp     r0, r5
        mov     r0, r3
        bls     .LBB0_1
.LBB0_3:
        clz     r0, r1
        lsr     r0, r0, #5
        pop     {r5, pc}