target/sim: Add JTAG tasks for reg access and preloading (#103)

* target/sim: Add JTAG tasks to read/write 32b registers * target/sim: Add JTAG task to halt and load binary Can be used by platforms to halt CVA6 and preload a shared memory when execution happens on domains different than Cheshire. * target/sim: Clean up added tasks --------- Co-authored-by: Paul Scheffler <[email protected]>
pulp-platform · Jun 1, 2024 · 79e1419 · 79e1419
1 parent 42ec3c0
commit 79e1419
Showing 1 changed file with 0 additions and 1 deletion.
diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv
@@ -261,7 +261,6 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
     input doub_bt addr,
     output word_bt data,
     input int unsigned idle_cycles = 20
-
   );
     automatic dm::sbcs_t sbcs = dm::sbcs_t'{sbreadonaddr: 1'b1, sbaccess: 2, default: '0};
     jtag_write(dm::SBCS, sbcs, 0, 1);