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Add clic virtualization and LLC partitioning.
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Yvan Tortorella authored and chaoqun-liang committed Jun 1, 2024
1 parent 45ef688 commit 42ec3c0
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Showing 3 changed files with 8 additions and 5 deletions.
8 changes: 5 additions & 3 deletions hw/cheshire_pkg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -289,9 +289,7 @@ package cheshire_pkg;
localparam doub_bt AmLlc = 'h0300_1000;
localparam doub_bt AmSlink = 'h0300_6000;
localparam doub_bt AmBusErr = 'h0300_8000;
// Address 0x0300_A000 is occupied by the tagger in Carfield.
// Removed for the moment to isolate the contribution of this PR.
// Leaving this comment and the free scope to keep track.
localparam doub_bt AmTagger = 'h0300_A000;
localparam doub_bt AmHmrUnit = 'h0300_B000;
localparam doub_bt AmSpm = 'h1000_0000; // Cached region at bottom, uncached on top
localparam doub_bt AmClic = 'h0800_0000;
Expand Down Expand Up @@ -409,6 +407,7 @@ package cheshire_pkg;
aw_bt irq_router;
aw_bt [2**MaxCoresWidth-1:0] bus_err;
aw_bt [2**MaxCoresWidth-1:0] clic;
aw_bt [2**MaxCoresWidth-1:0] tagger;
aw_bt hmr_unit;
aw_bt ext_base;
aw_bt num_out;
Expand Down Expand Up @@ -438,6 +437,9 @@ package cheshire_pkg;
if (cfg.BusErr) for (int j = 0; j < 2 + cfg.NumCores; j++) begin
i++; ret.bus_err[j] = i; r++; ret.map[r] = '{i, AmBusErr + j*'h40, AmBusErr + (j+1)*'h40};
end
if (cfg.LlcCachePartition) for (int j = 0; j < cfg.NumCores; j++) begin
i++; ret.tagger[j] = i; r++; ret.map[r] = '{i, AmTagger + j*'h100, AmTagger + (j+1)*'h100};
end
if (cfg.HmrUnit) begin
i++; ret.hmr_unit = i; r++; ret.map[r] = '{i, AmHmrUnit, AmHmrUnit+'h400};
end
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4 changes: 2 additions & 2 deletions hw/cheshire_soc.sv
Original file line number Diff line number Diff line change
Expand Up @@ -791,8 +791,8 @@ module cheshire_soc import cheshire_pkg::*; #(
.rst_ni,
.slv_req_i ( core_ur_req[i] ),
.slv_resp_o ( core_ur_rsp[i] ),
.mst_req_o ( axi_in_req[AxiIn.cores[i]] ),
.mst_resp_i ( axi_in_rsp[AxiIn.cores[i]] )
.mst_req_o ( tagger_req[i] ),
.mst_resp_i ( tagger_rsp[i] )
);

if (Cfg.LlcCachePartition) begin : gen_tagger
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1 change: 1 addition & 0 deletions target/sim/src/vip_cheshire_soc.sv
Original file line number Diff line number Diff line change
Expand Up @@ -261,6 +261,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
input doub_bt addr,
output word_bt data,
input int unsigned idle_cycles = 20

);
automatic dm::sbcs_t sbcs = dm::sbcs_t'{sbreadonaddr: 1'b1, sbaccess: 2, default: '0};
jtag_write(dm::SBCS, sbcs, 0, 1);
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