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target/sim: Clean up added tasks
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@paulsc96
paulsc96 committed Feb 23, 2024
1 parent 33ad6a7 commit 36ffd2c
Showing 1 changed file with 28 additions and 70 deletions.
98 changes: 28 additions & 70 deletions target/sim/src/vip_cheshire_soc.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -238,6 +238,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
jtag_dbg.read_dmi_exp_backoff(dm::SBData0, data);
end while (~data[0]);
endtask

// Initialize the debug module
task automatic jtag_init;
jtag_idcode_t idcode;
Expand All @@ -256,87 +257,39 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
$display("[JTAG] Initialization success");
endtask

// Halt the core and preload a binary
task automatic jtag_elf_halt_load(input string binary, output doub_bt entry );
dm::dmstatus_t status;
// Wait until bootrom initialized LLC
if (DutCfg.LlcNotBypass) begin
word_bt regval;
$display("[JTAG] Wait for LLC configuration");
jtag_poll_bit0(AmLlc + axi_llc_reg_pkg::AXI_LLC_CFG_SPM_LOW_OFFSET, regval, 20);
end
// Halt hart 0
jtag_write(dm::DMControl, dm::dmcontrol_t'{haltreq: 1, dmactive: 1, default: '0});
do jtag_dbg.read_dmi_exp_backoff(dm::DMStatus, status);
while (~status.allhalted);
$display("[JTAG] Halted hart 0");
// Preload binary
jtag_elf_preload(binary, entry);
endtask

task automatic jtag_write_reg32(input logic [31:0] start_addr, logic [63:0] value);
logic [31:0] rdata;

automatic dm::sbcs_t sbcs = dm::sbcs_t'{sbreadonaddr: 1'b1, sbaccess: 2, default: '0};

$display("[JTAG] Start writing at %x ", start_addr);
jtag_write(dm::SBCS, sbcs, 0, 1);

// Write address
$display("[JTAG] Start writing address");
jtag_write(dm::SBAddress1, 'h0);
jtag_write(dm::SBAddress0, start_addr);

// Write data
$display("[JTAG] Start writing data");
jtag_write(dm::SBData0, value[31:0]);

endtask

task automatic jtag_read_reg32(
input logic [31:0] addr,
output logic [31:0] data,
input int unsigned idle_cycles
input doub_bt addr,
output word_bt data,
input int unsigned idle_cycles = 20
);
automatic dm::sbcs_t sbcs = dm::sbcs_t'{sbreadonaddr: 1'b1, sbaccess: 2, default: '0};
jtag_write(dm::SBCS, sbcs, 0, 1);
jtag_write(dm::SBAddress1, 'h0);
jtag_write(dm::SBAddress1, addr[63:32]);
jtag_write(dm::SBAddress0, addr[31:0]);
jtag_dbg.wait_idle(idle_cycles);
jtag_dbg.read_dmi_exp_backoff(dm::SBData0, data);
$display("[JTAG] Read 0x%h from 0x%h", data, addr);
endtask

task automatic jtag_write_reg(input logic [31:0] start_addr, input doub_bt value);
logic [63:0] rdata;

$display("[JTAG] Start writing at %x ", start_addr);
jtag_write(dm::SBCS, JtagInitSbcs, 1, 1);
// Write address
jtag_write(dm::SBAddress0, start_addr);
// Write data
jtag_write(dm::SBData1, value[63:32]);
jtag_write(dm::SBData0, value[31:0]);

//Check correctess
jtag_read_reg(start_addr, rdata, 20);
if(rdata!=value) begin
$fatal(1,"rdata at %x: %x" , start_addr, rdata);
end else begin
$display("W/R sanity check at %x ok! : %x", start_addr, rdata);
end
endtask

task automatic jtag_read_reg(
task automatic jtag_write_reg32(
input doub_bt addr,
output word_bt data,
input int unsigned idle_cycles
input word_bt data,
input bit check_write,
input int unsigned check_write_wait_cycles = 20
);
automatic dm::sbcs_t sbcs = dm::sbcs_t'{sbreadonaddr: 1'b1, sbaccess: 2, default: '0};
automatic dm::sbcs_t sbcs = dm::sbcs_t'{sbaccess: 2, default: '0};
$display(1,"[JTAG] Writing 0x%h to 0x%h", data, addr, rdata);
jtag_write(dm::SBCS, sbcs, 0, 1);
jtag_write(dm::SBAddress1, addr[63:32]);
jtag_write(dm::SBAddress0, addr[31:0]);
jtag_dbg.wait_idle(idle_cycles);
jtag_dbg.read_dmi_exp_backoff(dm::SBData0, data);
jtag_write(dm::SBData0, data);
jtag_dbg.wait_idle(check_write_wait_cycles);
if (check_write) begin
word_bt rdata;
jtag_read_reg32(addr, rdata);
if (rdata != data) $fatal(1,"[JTAG] - Read back incorrect data 0x%h!", rdata);
else $display("[JTAG] - Read back correct data");
end
endtask

// Load a binary
Expand Down Expand Up @@ -365,10 +318,9 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
$display("[JTAG] Preload complete");
endtask

// Run a binary
task automatic jtag_elf_run(input string binary);
// Halt the core and preload a binary
task automatic jtag_elf_halt_load(input string binary, output doub_bt entry);
dm::dmstatus_t status;
doub_bt entry;
// Wait until bootrom initialized LLC
if (DutCfg.LlcNotBypass) begin
word_bt regval;
Expand All @@ -382,6 +334,12 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
$display("[JTAG] Halted hart 0");
// Preload binary
jtag_elf_preload(binary, entry);
endtask

// Run a binary
task automatic jtag_elf_run(input string binary);
doub_bt entry;
jtag_elf_halt_load(binary, entry);
// Repoint execution
jtag_write(dm::Data1, entry[63:32]);
jtag_write(dm::Data0, entry[31:0]);
Expand Down

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