Skip to content

Commit

Permalink
target/sim: Add JTAG task to halt and load binary
Browse files Browse the repository at this point in the history
* Can be used by platforms to halt CVA6 and preload a shared memory when
execution happens on domains different than Cheshire.
  • Loading branch information
alex96295 committed Feb 14, 2024
1 parent 67f0e7f commit 33ad6a7
Showing 1 changed file with 18 additions and 0 deletions.
18 changes: 18 additions & 0 deletions target/sim/src/vip_cheshire_soc.sv
Original file line number Diff line number Diff line change
Expand Up @@ -256,6 +256,24 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
$display("[JTAG] Initialization success");
endtask

// Halt the core and preload a binary
task automatic jtag_elf_halt_load(input string binary, output doub_bt entry );
dm::dmstatus_t status;
// Wait until bootrom initialized LLC
if (DutCfg.LlcNotBypass) begin
word_bt regval;
$display("[JTAG] Wait for LLC configuration");
jtag_poll_bit0(AmLlc + axi_llc_reg_pkg::AXI_LLC_CFG_SPM_LOW_OFFSET, regval, 20);
end
// Halt hart 0
jtag_write(dm::DMControl, dm::dmcontrol_t'{haltreq: 1, dmactive: 1, default: '0});
do jtag_dbg.read_dmi_exp_backoff(dm::DMStatus, status);
while (~status.allhalted);
$display("[JTAG] Halted hart 0");
// Preload binary
jtag_elf_preload(binary, entry);
endtask

task automatic jtag_write_reg32(input logic [31:0] start_addr, logic [63:0] value);
logic [31:0] rdata;

Expand Down

0 comments on commit 33ad6a7

Please sign in to comment.