Add NRST_SYNCHRONIZER

Asynchronous Reset (Active LOW) Synchronizer

05_NRST_SYNCHRONIZER/NRST_SYNCHRONIZER.v

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+/*-----------------------------------------------------------------------------
+* NRST_SYNCHRONIZER.v
+*
+* Asynchronous Reset (Active LOW) Synchronizer
+*
+* Version: 1.00
+* Author : AUDIY
+* Date   : 2024/12/16
+* 
+* Port
+*   Input
+*       CLK_I  : Data Clock Input
+*       NRST_I : Asynchronous Reset Input (Active LOW)
+*
+*   Output
+*       NRST_O : Reset Output (Synchronized when it negated.)
+*
+* Parameters
+*   STAGES: Synchronization Stage Length (Default: 2)
+*
+* License under CERN-OHL-P v2
+--------------------------------------------------------------------------------
+| Copyright AUDIY 2024.                                                        |
+|                                                                              |
+| This source describes Open Hardware and is licensed under the CERN-OHL-P v2. |
+|                                                                              |
+| You may redistribute and modify this source and make products using it under |
+| the terms of the CERN-OHL-P v2 (https:/cern.ch/cern-ohl).                    |
+|                                                                              |
+| This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,          |
+| INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A         |
+| PARTICULAR PURPOSE. Please see the CERN-OHL-P v2 for applicable conditions.  |
+--------------------------------------------------------------------------------
+*
+-----------------------------------------------------------------------------*/
+`default_nettype none
+module NRST_SYNCHRONIZER #(
+    parameter STAGES = 2
+) (
+    input  wire CLK_I ,
+    input  wire NRST_I,
+    output wire NRST_O
+);
+
+    reg [STAGES - 1:0] NRST_SYNC = {(STAGES){1'b0}};
+
+    always @(posedge CLK_I or negedge NRST_I ) begin
+        if (!NRST_I) begin
+            /* When NRST_I is asserted, assert reset immediately */
+            NRST_SYNC <= {(STAGES){1'b0}};
+        end else begin
+            /* Negate reset synchronized with CLK_I */
+            NRST_SYNC <= {NRST_SYNC[STAGES - 2:0], 1'b1};
+        end
+    end
+
+    assign NRST_O = NRST_SYNC[STAGES - 1];
+
+endmodule

05_NRST_SYNCHRONIZER/NRST_SYNCHRONIZER_tb.v

@@ -0,0 +1,58 @@
+/*-----------------------------------------------------------------------------
+* NRST_SYNCHRONIZER_tb.v
+*
+* Testbench for NRST_SYNCHRONIZER.sv
+*
+* Version: 1.00
+* Author : AUDIY
+* Date   : 2024/12/16
+*
+* License under CERN-OHL-P v2
+--------------------------------------------------------------------------------
+| Copyright AUDIY 2024.                                                        |
+|                                                                              |
+| This source describes Open Hardware and is licensed under the CERN-OHL-P v2. |
+|                                                                              |
+| You may redistribute and modify this source and make products using it under |
+| the terms of the CERN-OHL-P v2 (https:/cern.ch/cern-ohl).                    |
+|                                                                              |
+| This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,          |
+| INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A         |
+| PARTICULAR PURPOSE. Please see the CERN-OHL-P v2 for applicable conditions.  |
+--------------------------------------------------------------------------------
+*
+-----------------------------------------------------------------------------*/
+`default_nettype none
+`timescale 1ns/1ps
+
+module NRST_SYNCHRONIZER_tb ();
+
+    localparam  STAGES = 3;
+
+    reg CLK_I = 1'b0;
+    reg NRST_I = 1'b1;
+    wire NRST_O;
+
+    NRST_SYNCHRONIZER #(
+        .STAGES(STAGES)
+    ) u0 (
+        .CLK_I(CLK_I),
+        .NRST_I(NRST_I),
+        .NRST_O(NRST_O)
+    );
+
+    initial begin
+        $dumpfile("NRST_SYNCHRONIZER.vcd");
+        $dumpvars(0, NRST_SYNCHRONIZER_tb);
+
+        #23 NRST_I = 1'b0;
+        #14 NRST_I = 1'b1;
+
+        #64 $finish();
+    end
+
+    always begin
+        #2 CLK_I <= ~CLK_I;
+    end
+
+endmodule