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Update README.md
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@AUDIY
AUDIY authored Dec 16, 2024
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Verilog IP that AUDIY originally designed.

Code reviews are welcome!

## Notice: This repository is no longer maintained.
The author made a decision to shift HDL from Verilog to SystemVerilog.
So it means that the author doesn't maintain and use modules in this repository.

The new IP repository written in SystemVerilog is [AUDIY_SV_IP](https://github.com/AUDIY/AUDIY_SV_IP)

Thanks.

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