Add support Flash QSPI on S32ZE #434
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congnguyenhuu
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Could you pls explain why these values are chosen: |
these value is maximum value frequency that is configurable in range of QSPI frequency |
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@dleach02 this is ready for merging, zephyr side approved by assignee |
This is the Mem_ExFls Qspi baremetal driver for s32ze Signed-off-by: Cong Nguyen Huu <[email protected]>
Use zephyr .nocache section for non-cacheable variables. Signed-off-by: Cong Nguyen Huu <[email protected]>
Code autogenerated with S32 Design Studio for s32ze Signed-off-by: Cong Nguyen Huu <[email protected]>
Adapt macros that are used in the QSPI memc and QSPI flash shim drivers. Signed-off-by: Cong Nguyen Huu <[email protected]>
Select PERIPHPLL_DFS0 clock as QSPI0 clock source Select PERIPHPLL_DFS2 clock as QSPI1 clock source Update QSPI dividers so that value clocks: P4_QSPI0_1X_CLK is 200 MHz P4_QSPI0_2X_CLK is 400 MHz P4_QSPI1_1X_CLK is 150 MHz P4_QSPI1_2X_CLK is 300 MHz Signed-off-by: Cong Nguyen Huu <[email protected]>
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I rebased the latest hal_nxp |
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Add baremetal driver for QSPI on S32ZE devices and headers for QSPI on SoC S32Z270