Add bank wide GPIO TRAPs for read/write

[rrbutani]

what

Currently we offer per pin GPIO mode setting and read/write TRAPs:

core/os/src/traps.rs

Lines 12 to 18 in 5e0f0eb

	//! | **`0x30`** | [GPIO_INPUT] | [`R0`] - [pin][gpin] # | `n` bit | Puts a [GPIO] [pin][gpin] in [Input mode][gInput]. |
	//! | **`0x31`** | [GPIO_OUTPUT] | [`R0`] - [pin][gpin] # | `n` bit | Puts a [GPIO] [pin][gpin] in [Output mode][gOutput]. |
	//! | **`0x32`** | [GPIO_INTERRUPT] | [`R0`] - [pin][gpin] # <br>[`R1`] - address of ISR | `n` bit | Puts a [GPIO] in [Interrupt mode][gInterrupt] and sets the ISR. |
	//! | **`0x33`** | [GPIO_DISABLED] | [`R0`] - [pin][gpin] # | `n` bit | Puts a [GPIO] [pin][gpin] in [Disabled mode][gDisabled]. |
	//! | **`0x34`** | [GPIO_GET_MODE] | [`R0`] - [pin][gpin] # | [`R0`] - [GPIO mode] <br>`n` bit | Returns the [mode][gmode] of a [GPIO] [pin][gpin]. |
	//! | **`0x35`** | [GPIO_WRITE] | [`R0`] - [pin][gpin] # <br>[`R1`] - data to write | `n` bit | Writes to a [GPIO] [pin][gpin] in [Output mode][gOutput]. |
	//! | **`0x36`** | [GPIO_READ] | [`R0`] - [pin][gpin] # | [`R0`] - data from pin <br>`n` bit | Reads data from a [GPIO] [pin][gpin]. |

We should also offer bank wide read/write TRAPs for users that are concerned with performance. These should access the port wide GPIO mem-mapped register:

core/baseline-sim/src/mem_mapped.rs

Line 46 in 8404e86

pub const GPIODR_ADDR: Addr = GPIO_MEM_MAPPED_BASE + GPIO_PIN_ADDRS * 8 + 0;

That in turn shells out to Gpio::read_all/Gpio::write_all:

core/baseline-sim/src/mem_mapped.rs

Lines 596 to 631 in 8404e86

	where
	I: InstructionInterpreterPeripheralAccess<'a>,
	<I as Deref>::Target: Peripherals<'a>,
	{
	use lc3_traits::peripherals::gpio::GpioState::*;
	let state = match value.bits(0..1) {
	0 => Disabled,
	1 => Output,
	2 => Input,
	3 => Interrupt,
	_ => unreachable!()
	};
	match Gpio::set_state(interp.get_peripherals_mut(), $pin, state) {
	Ok(()) => Ok(()),
	Err(err) => {
	interp.set_error(Error::from(err));
	Ok(())
	}
	}
	}
	}
	impl Interrupt for $cr {
	const INT_VEC: u8 = $int_vec;
	const PRIORITY: u8 = GPIO_INT_PRIORITY;
	fn interrupt_ready<'a, I>(interp: &I) -> bool
	where
	I: InstructionInterpreterPeripheralAccess<'a>,
	<I as Deref>::Target: Peripherals<'a>,
	{
	Gpio::interrupt_occurred(interp.get_peripherals(), $pin)
	}
	fn interrupt_enabled<'a, I>(interp: &I) -> bool

steps

• add TRAP x37: GPIO_READ_BANK
• add TRAP x38: GPIO_WRITE_BANK
• after Add two extra GPIO banks to the peripherals #178 goes through, update the above to support multiple banks
• add documentation for these TRAPs here
• add tests for these TRAPs to the GPIO trap tests
• add a µbench style benchmark to the tm4c repo:
  • comparing:
    • raw bank register access
    • raw per pin register access
    • TRAP bank access
    • TRAP per pin access
  • in a microbenchmark that just reads/writes the 8 pins in bank A

where

branch: feat/bank-wide-gpio-traps

open questions

State checking/error handling for the GPIO_READ_BANK/GPIO_WRITE_BANK TRAPs?

• I think we can get away with essentially nothing, just checking that the bank number given is in bounds
• The mem mapped register for the bank is pretty forgiving in the accesses/writes it allows (0s when you read disabled pins, discarded writes when you write to non-outputs) and I think this is the behavior that we want for the TRAPs too.