Skip to content
View skristiansson's full-sized avatar

Organizations

@openrisc

Block or report skristiansson

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. i2s i2s Public

    i2s core, with support for both transmit and receive

    Verilog 29 11

  2. wb_sdram_ctrl wb_sdram_ctrl Public

    SDRAM controller with multiple wishbone slave ports

    Verilog 28 12

  3. ar100-info ar100-info Public

    C 13 3

  4. llvm-or1k llvm-or1k Public

    LLVM backend for OpenRISC 1000

    C++ 12 13

  5. diila diila Public

    A Device Independent Integrated Logic Analyzer

    Verilog 11 1

  6. clang-or1k clang-or1k Public

    Clang for OpenRISC 1000

    C++ 7 9