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Verilog source for the extension #179

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DuyTrandeLion opened this issue Nov 11, 2022 · 1 comment

DuyTrandeLion commented Nov 11, 2022

Hello, may I ask where can I find the verilog source for this extension? Thanks.

AaronKutch commented Dec 23, 2022

there is no definitive "source" for the extensions but there are reference implementations https://github.com/riscv/riscv-bitmanip/tree/main-history/verilog

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