RgGen Sample Testbench

This is an sample testbench to demonstrate integrating UVM RAL model generated by RgGen into UVM based testbench.

Preparation

This env uses flgen to generate *.f files which are given to simulator tools. Therefore, you need to install the tool before using this env. See its repository for details.

DUT

In this testbech, CSR modules generated by RgGen are used as DUT and there are three types of DUT:

• DUT with AMBA APB iterface
  • https://github.com/rggen/rggen-sample-testbench/tree/master/rtl/apb
• DUT with AMBA AXI4-Lite interface
  • https://github.com/rggen/rggen-sample-testbench/tree/master/rtl/axi4lite
• DUT with wishbone interface
  • https://github.com/rggen/rggen-sample-testbench/tree/master/rtl/wishbone

Sample Testcases

This testbench inclues three sample testcases invoking pre-defined test sequences.

Test Name	Test Sequence
ral_hw_reset_test	uvm_reg_hw_reset_seq
ral_bit_bash_test	uvm_reg_bit_bash_seq
ral_access_test	uvm_reg_access_seq

Usage

Setup

This testbench depends on some submodules so you need to get them from GitHub repositries. To do this, hit the command below on the root of this repositly.

$ cd rggen-sample-testbench
$ ./setup_submodules.sh

If execution of above commands failed you need to get them from GitHub repositlies directly and set some environment variables.

$ git clone https://github.com/taichi-ishitani/tue.git
$ export TUE_HOME=`pwd`/tue
$ git clone https://github.com/taichi-ishitani/tvip-common.git
$ export TVIP_COMMON_HOME=`pwd`/tvip-common
$ git clone https://github.com/taichi-ishitani/tvip-apb.git
$ export TVIP_APB_HOME=`pwd`/tvip-apb
$ git clone https://github.com/taichi-ishitani/tvip-axi.git
$ export TVIP_APB_HOME=`pwd`/tvip-axi
$ git clone https://github.com/rggen/rggen-sv-rtl.git
$ export RGGEN_SV_RTL_ROOT=`pwd`/rggen-sv-rtl
$ git clone https://github.com/rggen/rggen-sv-ral.git
$ export RGGEN_SV_RTL_ROOT=`pwd`/rggen-sv-ral
$ git clone https://github.com/rggen/rggen-verilog-rtl.git
$ export RGGEN_VERILOG_RTL_ROOT=`pwd`/rggen-verilog-rtl
$ git clone https://github.com/rggen/rggen-vhdl-rtl.git
$ export RGGEN_VHDL_RTL_ROOT=`pwd`/rggen-vhdl-rtl

Run Simulation

Synopsys VCS simulator, Cadence Xcelium simulator, Metrics DSim simulator and AMD Vivado simulator are supported.

1. Move to the work directry

   • for DUT with AMBA APB interfac
     • sim/apb/systemverilog
     • sim/apb/verilog
     • sim/apb/veryl
     • sim/apb/vhdl
   • for DUT with AMBA AXI4-Lite interface
     • sim/axi4lite/systemverilog
     • sim/axi4lite/verilog
     • sim/axi4lite/veryl
     • sim/axi4lite/vhdl
   • for DUT with wishbone interface
     • sim/wishbone/systemverilog
     • sim/wishbone/verilog
     • sim/wishbone/veryl
     • sim/wishbone/vhdl

2. Hit make command on the work directry

$ make

By default, all sample testcases will be execluted by VCS simulator. If you want to use Xcelium, DSim or Vivado simulator, add SIMULATOR option to makefile command.

• For Xcelium:

$ make SIMULATOR=xcelium

• For DSim

$ make SIMULATOR=dsim

• For Vivado:

$ make SIMULATOR=vivado

If you want to execute an specific testcase then you need to give its name to make command like below.

$ make ral_bit_bash_test

The GUI option is to enable the inteructive debug environment. To invoke the GUI frontend, give this option to make command like below.

• Frontend: DVE

$ make ral_bit_bash_test GUI=dve

• Frontend: Verdi

$ make ral_bit_bash_test GUI=verdi

• Frontend: Indago

$ make ral_bit_bash_test SIMULATOR=xcelium GUI=indago

• Frontend: Vivado

$ make ral_bit_bash_test SIMULATOR=vivado GUI=on

Contact

You can post your questions, feedbacks, bug reports, etc. by using following ways.

• GitHub Issue Tracker
• Chat Room
• Mailing List
• Mail

Copyright & License

Copyright © 2019-2024 Taichi Ishitani. This testbench is licensed under the MIT License, see LICENSE for futher detils.