[sw] added initial support for interface with memory island

hw/system/spatz_cluster/cfg/flamingo.hjson

@@ -67,6 +67,10 @@
         // 0x8000_0000
         length: 2147483648
     },
+    l2: {
+        address: 2013265920,          // 0x78000000
+        length: 8388608               // 0x800000
+    },
     peripherals: {
     },
 

hw/system/spatz_cluster/src/spatz_cluster.sv

@@ -37,6 +37,8 @@ module spatz_cluster
     parameter int                     unsigned               AxiUserWidth                       = 1,
     /// Address from which to fetch the first instructions.
     parameter logic                            [31:0]        BootAddr                           = 32'h0,
+    /// Address to indicate start of L2
+    parameter logic                   [AxiAddrWidth-1:0]     L2Addr                             = 48'h0,
     /// The total amount of cores.
     parameter int                     unsigned               NrCores                            = 8,
     /// Data/TCDM memory depth per cut (in words).
@@ -403,8 +405,8 @@ module spatz_cluster
   // assign cluster_l2_start_address = cluster_periph_end_address + ClusterReserve * 1024;
   // assign cluster_l2_end_address   = cluster_l2_start_address   + ClusterL2Size * 1024;
   // TODO: change to calc base on cluster_base_addr_i
-  assign cluster_l2_start_address = 48'h5180_0000;
-  assign cluster_l2_end_address   = 48'h5200_0000;
+  assign cluster_l2_start_address = L2Addr; //48'h5180_0000;
+  assign cluster_l2_end_address   = 48'h7880_0000; //48'h5200_0000;
 
   // ----------------
   // Wire Definitions

hw/system/spatz_cluster/src/spatz_cluster_wrapper.sv.tpl

@@ -529,6 +529,7 @@ module ${cfg['name']}_wrapper
     .AxiIdWidthOut (spatz_cluster_pkg::IwcAxiIdOutWidth),
     .AxiUserWidth (AxiUserWidth),
     .BootAddr (${to_sv_hex(cfg['boot_addr'], 32)}),
+    .L2Addr   (48'h78000000),
     .ClusterPeriphSize (${cfg['cluster_periph_size']}),
     .NrCores (${cfg['nr_cores']}),
     .TCDMDepth (${cfg['tcdm']['depth']}),
@@ -590,8 +591,8 @@ module ${cfg['name']}_wrapper
     // AXI Master Port
     .axi_out_req_o  ( axi_from_cluster_iwc_req ),
     .axi_out_resp_i ( axi_from_cluster_iwc_resp ),
-    .axi_out_l2_req_o  ( /* unused now */ ),
-    .axi_out_l2_resp_i ( '0 )
+    .axi_out_l2_req_o  ( axi_from_cluster_l2_req ),
+    .axi_out_l2_resp_i ( axi_from_cluster_l2_resp )
   );
 
   // Assertions

hw/system/spatz_cluster/tb/testbench.sv.tpl

@@ -28,8 +28,13 @@ module testharness (
   localparam NumAXISlaves = 2;
   localparam NumRules     = NumAXISlaves-1;
 
+  // Spatz wide port to SoC (currently dram)
   spatz_axi_out_req_t  axi_from_cluster_req;
   spatz_axi_out_resp_t axi_from_cluster_resp;
+  // Spatz wide port to L2
+  spatz_axi_out_req_t  axi_l2_req;
+  spatz_axi_out_resp_t axi_l2_resp;
+  // From SoC to Spatz
   spatz_axi_in_req_t   axi_to_cluster_req;
   spatz_axi_in_resp_t  axi_to_cluster_resp;
 
@@ -205,8 +210,8 @@ module testharness (
 % else:
     .axi_out_req_o   (axi_from_cluster_req ),
     .axi_out_resp_i  (axi_from_cluster_resp),
-    .axi_out_l2_req_o  ( ),
-    .axi_out_l2_resp_i  ('0),
+    .axi_out_l2_req_o   ( axi_l2_req ),
+    .axi_out_l2_resp_i  ( axi_l2_resp ),
     .axi_in_req_i    (axi_to_cluster_req   ),
     .axi_in_resp_o   (axi_to_cluster_resp  ),
 % endif
@@ -342,4 +347,19 @@ module testharness (
     .rsp_o (axi_from_cluster_resp)
   );
 
+  // Wide port into simulation memory.
+  tb_memory_axi #(
+    .AxiAddrWidth ( SpatzAxiAddrWidth    ),
+    .AxiDataWidth ( SpatzAxiDataWidth    ),
+    .AxiIdWidth   ( SpatzAxiIdOutWidth   ),
+    .AxiUserWidth ( SpatzAxiUserWidth    ),
+    .req_t        ( spatz_axi_out_req_t  ),
+    .rsp_t        ( spatz_axi_out_resp_t )
+  ) i_l2mem (
+    .clk_i (clk_i                ),
+    .rst_ni(rst_ni               ),
+    .req_i (axi_l2_req           ),
+    .rsp_o (axi_l2_resp          )
+  );
+
 endmodule : testharness

hw/system/spatz_cluster/test/link.ld.tpl

@@ -5,15 +5,17 @@
 OUTPUT_ARCH( "riscv" )
 ENTRY(_start)
 <% dram_address = cfg['dram']['address']; %>
+<% l2_address = cfg['l2']['address']; %>
 MEMORY
 {
     DRAM (rwxai)  : ORIGIN = ${dram_address}, LENGTH = ${cfg['dram']['length']}
+    L2 (rwxai)  : ORIGIN = ${cfg['l2']['address']}, LENGTH = ${cfg['l2']['length']}
     L1 (rw) : ORIGIN = ${l1_region[0]}, LENGTH = ${l1_region[1]}K
 }
 
 SECTIONS
 {
-  . = ${dram_address};
+  . = ${l2_address};
   .text.init : { *(.text.init) }
   . = ALIGN(0x1000);
   .tohost : { *(.tohost) }

sw/snRuntime/CMakeLists.txt

@@ -28,6 +28,8 @@ add_compile_options(-O3 -g -ffunction-sections)
 if(SNITCH_RUNTIME STREQUAL "snRuntime-cluster")
     set(MEM_DRAM_ORIGIN "0x80000000" CACHE STRING "Base address of external memory")
     set(MEM_DRAM_SIZE "0x80000000" CACHE STRING "Size of external memory")
+    set(L2_ORIGIN "0x78000000" CACHE STRING "Base address of L2 memory")
+    set(L2_SIZE   "0x78800000" CACHE STRING "Size of L2 memory")
 else()
     set(MEM_DRAM_ORIGIN "0x80000000" CACHE STRING "Base address of external memory")
     set(MEM_DRAM_SIZE "256M" CACHE STRING "Size of external memory")

sw/snRuntime/link/common.ld.in

@@ -7,7 +7,7 @@ ENTRY(_start)
 
 MEMORY
 {
-    DRAM (rwxa)  : ORIGIN = @MEM_DRAM_ORIGIN@, LENGTH = @MEM_DRAM_SIZE@
+    DRAM (rwxa)  : ORIGIN = @L2_ORIGIN@, LENGTH = @L2_SIZE@
 }
 
 SECTIONS