Skip to content

Commit

Permalink
Merge branch 'flamingo/l2support' into diyou/flamingo-perf
Browse files Browse the repository at this point in the history
  • Loading branch information
@DiyouS
DiyouS committed Dec 12, 2024
2 parents f7f6c42 + f6ced8a commit 1f19e33
Show file tree
Hide file tree
Showing 7 changed files with 41 additions and 11 deletions.
4 changes: 4 additions & 0 deletions hw/system/spatz_cluster/cfg/flamingo.hjson
View file
Original file line number Diff line number Diff line change
Expand Up @@ -67,6 +67,10 @@
// 0x8000_0000
length: 2147483648
},
l2: {
address: 1367343104, // 0x5180_0000
length: 8388608 // 0x5200_0000
},
peripherals: {
},

Expand Down
10 changes: 5 additions & 5 deletions hw/system/spatz_cluster/src/spatz_cluster.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,9 @@ module spatz_cluster
parameter int unsigned AxiUserWidth = 1,
/// Address from which to fetch the first instructions.
parameter logic [31:0] BootAddr = 32'h0,

Check warning on line 39 in hw/system/spatz_cluster/src/spatz_cluster.sv

View workflow job for this annotation

GitHub Actions / verible-verilog-lint

[verible-verilog-lint] hw/system/spatz_cluster/src/spatz_cluster.sv#L39 

Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]"  location:{path:"hw/system/spatz_cluster/src/spatz_cluster.sv"  range:{start:{line:39  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
/// Address to indicate start of L2
parameter logic [AxiAddrWidth-1:0] L2Addr = 48'h0,

Check warning on line 41 in hw/system/spatz_cluster/src/spatz_cluster.sv

View workflow job for this annotation

GitHub Actions / verible-verilog-lint

[verible-verilog-lint] hw/system/spatz_cluster/src/spatz_cluster.sv#L41 

Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]"  location:{path:"hw/system/spatz_cluster/src/spatz_cluster.sv"  range:{start:{line:41  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
parameter logic [AxiAddrWidth-1:0] L2Size = 48'h0,

Check warning on line 42 in hw/system/spatz_cluster/src/spatz_cluster.sv

View workflow job for this annotation

GitHub Actions / verible-verilog-lint

[verible-verilog-lint] hw/system/spatz_cluster/src/spatz_cluster.sv#L42 

Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]"  location:{path:"hw/system/spatz_cluster/src/spatz_cluster.sv"  range:{start:{line:42  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
/// The total amount of cores.
parameter int unsigned NrCores = 8,
/// Data/TCDM memory depth per cut (in words).
Expand Down Expand Up @@ -400,11 +403,8 @@ module spatz_cluster
localparam int unsigned ClusterReserve = 4096; // 4 MiB
localparam int unsigned ClusterL2Size = 8192; // 8 MiB
addr_t cluster_l2_start_address, cluster_l2_end_address;
// assign cluster_l2_start_address = cluster_periph_end_address + ClusterReserve * 1024;
// assign cluster_l2_end_address = cluster_l2_start_address + ClusterL2Size * 1024;
// TODO: change to calc base on cluster_base_addr_i
assign cluster_l2_start_address = 48'h5180_0000;
assign cluster_l2_end_address = 48'h5200_0000;
assign cluster_l2_start_address = L2Addr;
assign cluster_l2_end_address = L2Addr + L2Size;

// ----------------
// Wire Definitions
Expand Down
6 changes: 4 additions & 2 deletions hw/system/spatz_cluster/src/spatz_cluster_wrapper.sv.tpl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -529,6 +529,8 @@ module ${cfg['name']}_wrapper
.AxiIdWidthOut (spatz_cluster_pkg::IwcAxiIdOutWidth),
.AxiUserWidth (AxiUserWidth),
.BootAddr (${to_sv_hex(cfg['boot_addr'], 32)}),
.L2Addr (48'h5180_0000),
.L2Size (48'h80_0000),
.ClusterPeriphSize (${cfg['cluster_periph_size']}),
.NrCores (${cfg['nr_cores']}),
.TCDMDepth (${cfg['tcdm']['depth']}),
Expand Down Expand Up @@ -590,8 +592,8 @@ module ${cfg['name']}_wrapper
// AXI Master Port
.axi_out_req_o ( axi_from_cluster_iwc_req ),
.axi_out_resp_i ( axi_from_cluster_iwc_resp ),
.axi_out_l2_req_o ( /* unused now */ ),
.axi_out_l2_resp_i ( '0 )
.axi_out_l2_req_o ( axi_from_cluster_l2_req ),
.axi_out_l2_resp_i ( axi_from_cluster_l2_resp )
);

// Assertions
Expand Down
24 changes: 22 additions & 2 deletions hw/system/spatz_cluster/tb/testbench.sv.tpl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -28,8 +28,13 @@ module testharness (
localparam NumAXISlaves = 2;
localparam NumRules = NumAXISlaves-1;

// Spatz wide port to SoC (currently dram)
spatz_axi_out_req_t axi_from_cluster_req;
spatz_axi_out_resp_t axi_from_cluster_resp;
// Spatz wide port to L2
spatz_axi_out_req_t axi_l2_req;
spatz_axi_out_resp_t axi_l2_resp;
// From SoC to Spatz
spatz_axi_in_req_t axi_to_cluster_req;
spatz_axi_in_resp_t axi_to_cluster_resp;

Expand Down Expand Up @@ -205,8 +210,8 @@ module testharness (
% else:
.axi_out_req_o (axi_from_cluster_req ),
.axi_out_resp_i (axi_from_cluster_resp),
.axi_out_l2_req_o ( ),
.axi_out_l2_resp_i ('0),
.axi_out_l2_req_o ( axi_l2_req ),
.axi_out_l2_resp_i ( axi_l2_resp ),
.axi_in_req_i (axi_to_cluster_req ),
.axi_in_resp_o (axi_to_cluster_resp ),
% endif
Expand Down Expand Up @@ -342,4 +347,19 @@ module testharness (
.rsp_o (axi_from_cluster_resp)
);

// Wide port into simulation memory.
tb_memory_axi #(
.AxiAddrWidth ( SpatzAxiAddrWidth ),
.AxiDataWidth ( SpatzAxiDataWidth ),
.AxiIdWidth ( SpatzAxiIdOutWidth ),
.AxiUserWidth ( SpatzAxiUserWidth ),
.req_t ( spatz_axi_out_req_t ),
.rsp_t ( spatz_axi_out_resp_t )
) i_l2mem (
.clk_i (clk_i ),
.rst_ni(rst_ni ),
.req_i (axi_l2_req ),
.rsp_o (axi_l2_resp )
);

endmodule : testharness
4 changes: 3 additions & 1 deletion hw/system/spatz_cluster/test/link.ld.tpl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,15 +5,17 @@
OUTPUT_ARCH( "riscv" )
ENTRY(_start)
<% dram_address = cfg['dram']['address']; %>
<% l2_address = cfg['l2']['address']; %>
MEMORY
{
DRAM (rwxai) : ORIGIN = ${dram_address}, LENGTH = ${cfg['dram']['length']}
L2 (rwxai) : ORIGIN = ${cfg['l2']['address']}, LENGTH = ${cfg['l2']['length']}
L1 (rw) : ORIGIN = ${l1_region[0]}, LENGTH = ${l1_region[1]}K
}

SECTIONS
{
. = ${dram_address};
. = ${l2_address};
.text.init : { *(.text.init) }
. = ALIGN(0x1000);
.tohost : { *(.tohost) }
Expand Down
2 changes: 2 additions & 0 deletions sw/snRuntime/CMakeLists.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,8 @@ add_compile_options(-O3 -g -ffunction-sections)
if(SNITCH_RUNTIME STREQUAL "snRuntime-cluster")
set(MEM_DRAM_ORIGIN "0x80000000" CACHE STRING "Base address of external memory")
set(MEM_DRAM_SIZE "0x80000000" CACHE STRING "Size of external memory")
set(L2_ORIGIN "0x51800000" CACHE STRING "Base address of L2 memory")
set(L2_SIZE "0x800000" CACHE STRING "Size of L2 memory")
else()
set(MEM_DRAM_ORIGIN "0x80000000" CACHE STRING "Base address of external memory")
set(MEM_DRAM_SIZE "256M" CACHE STRING "Size of external memory")
Expand Down
2 changes: 1 addition & 1 deletion sw/snRuntime/link/common.ld.in
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ ENTRY(_start)

MEMORY
{
DRAM (rwxa) : ORIGIN = @MEM_DRAM_ORIGIN@, LENGTH = @MEM_DRAM_SIZE@
DRAM (rwxa) : ORIGIN = @L2_ORIGIN@, LENGTH = @L2_SIZE@
}

SECTIONS
Expand Down

0 comments on commit 1f19e33

Please sign in to comment.