PUSCH receiver kernels

.github/workflows/ci.yml

@@ -46,7 +46,7 @@ jobs:
         path: riscv-gnu-toolchain.tzst
 
   tc-llvm:
-    runs-on: ubuntu-20.04
+    runs-on: ubuntu-22.04
     steps:
     - uses: actions/checkout@v4
     - name: Recover the submodule commit hash
@@ -240,7 +240,7 @@ jobs:
         git diff --exit-code
 
   check-control-registers:
-    runs-on: ubuntu-20.04
+    runs-on: ubuntu-22.04
     steps:
     - uses: actions/checkout@v4
     - name: Install Python requirements
@@ -266,7 +266,7 @@ jobs:
   #  Build Software  #
   ####################
   build-apps-gcc:
-    runs-on: ubuntu-20.04
+    runs-on: ubuntu-22.04
     needs: tc-gcc
     strategy:
       matrix:
@@ -297,7 +297,7 @@ jobs:
         path: apps-gcc.tzst
 
   build-apps-llvm:
-    runs-on: ubuntu-20.04
+    runs-on: ubuntu-22.04
     needs: [tc-gcc, tc-llvm]
     strategy:
       matrix:
@@ -377,7 +377,7 @@ jobs:
   #  Run Software  #
   ##################
   run-apps-gcc:
-    runs-on: ubuntu-20.04
+    runs-on: ubuntu-22.04
     timeout-minutes: 20
     needs: [build-apps-gcc, riscv-isa-sim, verilator-model]
     strategy:
@@ -415,7 +415,7 @@ jobs:
         make trace
 
   run-apps-llvm:
-    runs-on: ubuntu-20.04
+    runs-on: ubuntu-22.04
     timeout-minutes: 20
     needs: [build-apps-llvm, riscv-isa-sim, verilator-model]
     strategy:
@@ -453,7 +453,7 @@ jobs:
         make trace
 
   run-apps-halide:
-    runs-on: ubuntu-20.04
+    runs-on: ubuntu-22.04
     timeout-minutes: 20
     needs: [build-apps-halide, riscv-isa-sim, verilator-model]
     strategy:

.github/workflows/lint.yml

@@ -11,7 +11,7 @@ jobs:
   # Check License #
   #################
   check-license:
-    runs-on: ubuntu-20.04
+    runs-on: ubuntu-22.04
     steps:
     - uses: actions/checkout@v4
     - name: Install Python requirements

CHANGELOG.md

@@ -51,6 +51,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 - Add pv.pack.h xpulpv2 instruction
 - Add a script to generate random data to preload the L2 memory
 - Add stack overflow simulator warning using dedicated CSR
+- Add mimo_mmse_f16 kernels
+- Add cmatmul_f16 kernels
+- Add cfft_radix4_f16 kernels
+- Add chest_f16 kernels
 
 ### Fixed
 - Measure the `wfi` stalls and stalls caused by `opc` properly

python-requirements.txt

@@ -15,3 +15,4 @@ progressbar2
 tabulate
 sympy
 scipy
+pyflexfloat

software/apps/baremetal/Makefile

@@ -20,8 +20,18 @@ APPS := $(patsubst $(APPS_DIR)/%/main.c,%,$(shell find $(APPS_DIR) -name "main.c
 BINARIES := $(addprefix $(BIN_DIR)/,$(APPS))
 ALL := $(APPS)
 
-ALL_GCC := $(filter-out matmul_f16 matmul_f32, $(ALL))
-ALL_LLVM := $(filter-out synth_i32 chest_q16 cfft_radix2_q16 cfft_radix4_q16, $(ALL))
+FP_APPS := axpy_f16 axpy_f32
+FP_APPS += cfft_radix4_f16 chest_f16 cholesky_f16
+FP_APPS += cmatmul_f16 matmul_f16 matmul_f32
+FP_APPS += dotp_f16 dotp_f32
+FP_APPS += mimo_mmse_f32 mimo_mmse_f16 mimo_mmse_f8 ofdm_f16
+
+I_APPS := synth_i32
+I_APPS += cfft_radix2_q16 cfft_radix4_q16 chest_q16 cholesky_q16 cholesky_q32
+I_APPS += cmatmul_q16 mimo_mmse_q16
+
+ALL_GCC := $(filter-out $(FP_APPS), $(ALL))
+ALL_LLVM := $(filter-out $(I_APPS), $(ALL))
 
 # Make all applications
 all: $(ALL_GCC)

software/apps/baremetal/axpy_f16/main.c

@@ -0,0 +1,60 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Author: Marco Bertuletti, ETH Zurich
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "dma.h"
+#include "encoding.h"
+#include "printf.h"
+#include "runtime.h"
+#include "synchronization.h"
+
+#include "data_axpy_f16.h"
+#define NUM_BANKS (NUM_CORES * BANKING_FACTOR)
+
+// Vectors for kernel computation
+__fp16 l1_X[array_N] __attribute__((aligned(NUM_BANKS), section(".l1_prio")));
+__fp16 l1_Y[array_N] __attribute__((aligned(NUM_BANKS), section(".l1_prio")));
+
+#include "baremetal/mempool_axpy_f16.h"
+#include "baremetal/mempool_checks.h"
+
+int main() {
+
+  uint32_t core_id = mempool_get_core_id();
+  uint32_t num_cores = mempool_get_core_count();
+  uint32_t time_init, time_end;
+  mempool_barrier_init(core_id);
+
+  time_init = 0;
+  time_end = 0;
+  if (core_id == 0) {
+    dma_memcpy_blocking(l1_X, l2_X, array_N * sizeof(int16_t));
+    dma_memcpy_blocking(l1_Y, l2_Y, array_N * sizeof(int16_t));
+  }
+  uint32_t register volatile a = *(uint32_t *)&(l2_A)&0x0000FFFF;
+  mempool_barrier(num_cores);
+
+  // PARALLEL, LOCAL ACCESSES
+  time_init = mempool_get_timer();
+  mempool_start_benchmark();
+  axpy_f16vecp_local_unrolled4(a, l1_X, l1_Y, array_N);
+  mempool_stop_benchmark();
+  time_end = mempool_get_timer();
+
+  mempool_barrier(num_cores);
+  // Check results
+  if (core_id == 0) {
+    uint32_t clock_cycles = (time_end - time_init);
+    printf("\nKernel execution takes %d clock cycles\n", clock_cycles);
+  }
+  mempool_check_f16(l1_Y, l2_Z, 100, 0.1f, 0);
+  mempool_barrier(num_cores);
+
+  return 0;
+}

software/apps/baremetal/axpy_f32/main.c

@@ -0,0 +1,59 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Author: Marco Bertuletti, ETH Zurich
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "dma.h"
+#include "encoding.h"
+#include "printf.h"
+#include "runtime.h"
+#include "synchronization.h"
+
+#include "data_axpy_f32.h"
+#define NUM_BANKS (NUM_CORES * BANKING_FACTOR)
+
+// Vectors for kernel computation
+float l1_X[array_N] __attribute__((aligned(NUM_BANKS), section(".l1_prio")));
+float l1_Y[array_N] __attribute__((aligned(NUM_BANKS), section(".l1_prio")));
+
+#include "baremetal/mempool_axpy_f32.h"
+#include "baremetal/mempool_checks.h"
+
+int main() {
+
+  uint32_t core_id = mempool_get_core_id();
+  uint32_t num_cores = mempool_get_core_count();
+  uint32_t time_init, time_end;
+  mempool_barrier_init(core_id);
+
+  time_init = 0;
+  time_end = 0;
+  if (core_id == 0) {
+    dma_memcpy_blocking(l1_X, l2_X, array_N * sizeof(int32_t));
+    dma_memcpy_blocking(l1_Y, l2_Y, array_N * sizeof(int32_t));
+  }
+  float register volatile a = l2_A;
+  mempool_barrier(num_cores);
+
+  // PARALLEL
+  time_init = mempool_get_timer();
+  mempool_start_benchmark();
+  axpy_f32p_local_unrolled4(a, l1_X, l1_Y, array_N);
+  mempool_stop_benchmark();
+  time_end = mempool_get_timer();
+
+  // Check results
+  if (core_id == 0) {
+    uint32_t clock_cycles = (time_end - time_init);
+    printf("\nKernel execution takes %d clock cycles\n", clock_cycles);
+  }
+  mempool_check_f32(l1_Y, l2_Z, 100, 0.1f, 0);
+  mempool_barrier(num_cores);
+
+  return 0;
+}

software/apps/baremetal/axpy_i32/main.c

@@ -16,7 +16,7 @@
 #include "runtime.h"
 #include "synchronization.h"
 
-#include "baremetal/mempool_axpy_i32p.h"
+#include "baremetal/mempool_axpy_i32.h"
 #include "baremetal/mempool_checks.h"
 #include "data_axpy_i32.h"
 
@@ -38,11 +38,12 @@ int main() {
     dma_memcpy_blocking(l1_Y, l2_Y, array_N * sizeof(int32_t));
     error = 0;
   }
+  register volatile int32_t a = l2_A;
   mempool_barrier(num_cores);
 
   // Benchmark
   mempool_start_benchmark();
-  calc_axpy_unloop_x4_localbank(l1_X, l1_Y, ALPHA, array_N, core_id, num_cores);
+  calc_axpy_unloop_x4_localbank(l1_X, l1_Y, a, array_N, core_id, num_cores);
   mempool_barrier(num_cores);
   mempool_stop_benchmark();