ibex: move includes to separate dir

pulp-platform · Oct 2, 2024 · 4e3acb4 · 4e3acb4
1 parent d897c00
commit 4e3acb4
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Showing 56 changed files with 1,370 additions and 61 deletions.
diff --git a/rtl/ibex/Bender.yml b/rtl/ibex/Bender.yml
@@ -13,16 +13,14 @@ sources:
 
   - target: not(all(any(test, ibex_include_tracer), not(ibex_exclude_tracer)))
     include_dirs:
-      - ./
-      - lowrisc_prim
+      - include/lowrisc_prim
 
     files:
       # Source files grouped in levels. Files in level 0 have no dependencies on files in this
       # package. Files in level 1 only depend on files in level 0, files in level 2 on files in
       # levels 1 and 0, etc. Files within a level are ordered alphabetically.
       # Level 0
       - ibex_pkg.sv
-      - lowrisc_prim/prim_assert.sv
       # Level 1
       - ibex_alu.sv
       - ibex_compressed_decoder.sv
@@ -50,15 +48,13 @@ sources:
   # formal interface so the tracer module works (`define RVFI).
   - target: all(any(test, ibex_include_tracer), not(ibex_exclude_tracer))  
     include_dirs:
-      - ./
-      - lowrisc_prim
+      - include/lowrisc_prim
     defines:
       RVFI: true
     files:
       # Level 0
       - ibex_pkg.sv
       - ibex_register_file_ff.sv
-      - lowrisc_prim/prim_assert.sv
       # Level 1
       - ibex_alu.sv
       - ibex_compressed_decoder.sv

diff --git a/rtl/ibex/ibex_branch_predict.sv b/rtl/ibex/ibex_branch_predict.sv
@@ -15,7 +15,7 @@
  * The predictor is entirely combinational but takes clk/rst_n signals for use by assertions.
  */
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module ibex_branch_predict (
   input  logic clk_i,

diff --git a/rtl/ibex/ibex_compressed_decoder.sv b/rtl/ibex/ibex_compressed_decoder.sv
@@ -11,7 +11,7 @@
  * assertions only.
  */
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module ibex_compressed_decoder (
     input  logic        clk_i,

diff --git a/rtl/ibex/ibex_controller.sv b/rtl/ibex/ibex_controller.sv
@@ -7,7 +7,7 @@
  * Main controller of the processor
  */
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module ibex_controller #(
     parameter bit WritebackStage  = 0,

diff --git a/rtl/ibex/ibex_core.sv b/rtl/ibex/ibex_core.sv
@@ -7,7 +7,7 @@
   `define RVFI
 `endif
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 /**
  * Top level module of the ibex RISC-V core

diff --git a/rtl/ibex/ibex_cs_registers.sv b/rtl/ibex/ibex_cs_registers.sv
@@ -10,7 +10,7 @@
  * Specification, draft version 1.11
  */
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module ibex_cs_registers #(
     parameter bit               DbgTriggerEn      = 0,

diff --git a/rtl/ibex/ibex_csr.sv b/rtl/ibex/ibex_csr.sv
@@ -6,7 +6,7 @@
  * Control / status register primitive
  */
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module ibex_csr #(
     parameter int unsigned    Width      = 32,

diff --git a/rtl/ibex/ibex_decoder.sv b/rtl/ibex/ibex_decoder.sv
@@ -11,7 +11,7 @@
  * assertions only.
  */
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module ibex_decoder #(
     parameter bit RV32E               = 0,

diff --git a/rtl/ibex/ibex_fetch_fifo.sv b/rtl/ibex/ibex_fetch_fifo.sv
@@ -10,7 +10,7 @@
  * clear_i clears the FIFO for the following cycle, including any new request
  */
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module ibex_fetch_fifo #(
   parameter int unsigned NUM_REQS = 2

diff --git a/rtl/ibex/ibex_icache.sv b/rtl/ibex/ibex_icache.sv
@@ -8,7 +8,7 @@
  * Provides an instruction cache along with cache management, instruction buffering and prefetching
  */
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module ibex_icache #(
   parameter bit          BranchPredictor = 1'b0,

diff --git a/rtl/ibex/ibex_id_stage.sv b/rtl/ibex/ibex_id_stage.sv
@@ -14,7 +14,7 @@
  * file.
  */
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module ibex_id_stage #(
     parameter bit               RV32E           = 0,

diff --git a/rtl/ibex/ibex_if_stage.sv b/rtl/ibex/ibex_if_stage.sv
@@ -10,7 +10,7 @@
  * the read instruction.
  */
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module ibex_if_stage #(
     parameter int unsigned DmHaltAddr        = 32'h1A110800,

diff --git a/rtl/ibex/ibex_load_store_unit.sv b/rtl/ibex/ibex_load_store_unit.sv
@@ -11,7 +11,7 @@
  * and to align bytes and halfwords.
  */
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module ibex_load_store_unit
 (

diff --git a/rtl/ibex/ibex_multdiv_fast.sv b/rtl/ibex/ibex_multdiv_fast.sv
@@ -12,7 +12,7 @@
  * 16x16 kernel multiplier and Long Division
  */
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module ibex_multdiv_fast #(
     parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast

diff --git a/rtl/ibex/ibex_multdiv_slow.sv b/rtl/ibex/ibex_multdiv_slow.sv
@@ -9,7 +9,7 @@
  * Baugh-Wooley multiplier and Long Division
  */
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module ibex_multdiv_slow
 (

diff --git a/rtl/ibex/ibex_wb_stage.sv b/rtl/ibex/ibex_wb_stage.sv
@@ -11,7 +11,7 @@
  * a simple passthrough to write data direct to the register file.
  */
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module ibex_wb_stage #(
   parameter bit WritebackStage = 1'b0

diff --git a/rtl/ibex/lowrisc_prim/prim_assert.sv → ...ibex/include/lowrisc_prim/prim_assert.svh b/rtl/ibex/lowrisc_prim/prim_assert.sv → ...ibex/include/lowrisc_prim/prim_assert.svh
@@ -6,8 +6,8 @@
 //  - Provides default clk and rst options to simplify code
 //  - Provides boiler plate template for common assertions
 
-`ifndef PRIM_ASSERT_SV
-`define PRIM_ASSERT_SV
+`ifndef PRIM_ASSERT_SVH
+`define PRIM_ASSERT_SVH
 
 ///////////////////
 // Helper macros //

diff --git a/...lowrisc_prim/prim_assert_dummy_macros.svh → ...lowrisc_prim/prim_assert_dummy_macros.svh b/...lowrisc_prim/prim_assert_dummy_macros.svh → ...lowrisc_prim/prim_assert_dummy_macros.svh
@@ -2,8 +2,8 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-// Macro bodies included by prim_assert.sv for tools that don't support assertions. See
-// prim_assert.sv for documentation for each of the macros.
+// Macro bodies included by prim_assert.svhh for tools that don't support assertions. See
+// prim_assert.svh for documentation for each of the macros.
 
 `define ASSERT_I(__name, __prop)
 `define ASSERT_INIT(__name, __prop)

diff --git a/...risc_prim/prim_assert_standard_macros.svh → ...risc_prim/prim_assert_standard_macros.svh b/...risc_prim/prim_assert_standard_macros.svh → ...risc_prim/prim_assert_standard_macros.svh
@@ -2,8 +2,8 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-// Macro bodies included by prim_assert.sv for tools that support full SystemVerilog and SVA syntax.
-// See prim_assert.sv for documentation for each of the macros.
+// Macro bodies included by prim_assert.svhh for tools that support full SystemVerilog and SVA syntax.
+// See prim_assert.svh for documentation for each of the macros.
 
 `define ASSERT_I(__name, __prop) \
   __name: assert (__prop)        \

diff --git a/...lowrisc_prim/prim_assert_yosys_macros.svh → ...lowrisc_prim/prim_assert_yosys_macros.svh b/...lowrisc_prim/prim_assert_yosys_macros.svh → ...lowrisc_prim/prim_assert_yosys_macros.svh
@@ -2,7 +2,7 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-// Macro bodies included by prim_assert.sv for formal verification with Yosys. See prim_assert.sv
+// Macro bodies included by prim_assert.svhh for formal verification with Yosys. See prim_assert.svh
 // for documentation for each of the macros.
 
 `define ASSERT_I(__name, __prop)    \

diff --git a/rtl/ibex/lowrisc_prim/prim_alert_receiver.sv b/rtl/ibex/lowrisc_prim/prim_alert_receiver.sv
@@ -27,7 +27,7 @@
 //
 // See also: prim_alert_sender, prim_diff_decode, alert_handler
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module prim_alert_receiver
   import prim_alert_pkg::*;

diff --git a/rtl/ibex/lowrisc_prim/prim_alert_sender.sv b/rtl/ibex/lowrisc_prim/prim_alert_sender.sv
@@ -28,7 +28,7 @@
 //
 // See also: prim_alert_receiver, prim_diff_decode, alert_handler
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module prim_alert_sender
   import prim_alert_pkg::*;

diff --git a/rtl/ibex/lowrisc_prim/prim_arbiter_fixed.sv b/rtl/ibex/lowrisc_prim/prim_arbiter_fixed.sv
@@ -11,7 +11,7 @@
 //
 // See also: prim_arbiter_ppc, prim_arbiter_tree
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module prim_arbiter_fixed #(
   parameter int N   = 8,

diff --git a/rtl/ibex/lowrisc_prim/prim_arbiter_ppc.sv b/rtl/ibex/lowrisc_prim/prim_arbiter_ppc.sv
@@ -23,7 +23,7 @@
 //
 // See also: prim_arbiter_tree
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module prim_arbiter_ppc #(
   parameter int unsigned N  = 8,

diff --git a/rtl/ibex/lowrisc_prim/prim_arbiter_tree.sv b/rtl/ibex/lowrisc_prim/prim_arbiter_tree.sv
@@ -30,7 +30,7 @@
 //
 // See also: prim_arbiter_ppc
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module prim_arbiter_tree #(
   parameter int N   = 8,

diff --git a/rtl/ibex/lowrisc_prim/prim_clock_div.sv b/rtl/ibex/lowrisc_prim/prim_clock_div.sv
@@ -2,7 +2,7 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module prim_clock_div #(
   parameter int Divisor = 2,

diff --git a/rtl/ibex/lowrisc_prim/prim_diff_decode.sv b/rtl/ibex/lowrisc_prim/prim_diff_decode.sv
@@ -15,7 +15,7 @@
 //
 // See also: prim_alert_sender, prim_alert_receiver, alert_handler
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module prim_diff_decode #(
   // enables additional synchronization logic

diff --git a/rtl/ibex/lowrisc_prim/prim_dom_and_2share.sv b/rtl/ibex/lowrisc_prim/prim_dom_and_2share.sv
@@ -23,7 +23,7 @@
 // Q1 = t{1,1} + sig(j>1,1)(...) + sig(j<1,1)(t{1,j} + Z{j})
 //    = a1&b1  + (0              + a1&b0 + z0)
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module prim_dom_and_2share #(
   parameter int DW = 64, // Input width

diff --git a/rtl/ibex/lowrisc_prim/prim_edn_req.sv b/rtl/ibex/lowrisc_prim/prim_edn_req.sv
@@ -11,7 +11,7 @@
 // requests.
 //
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module prim_edn_req
   import prim_alert_pkg::*;

diff --git a/rtl/ibex/lowrisc_prim/prim_esc_receiver.sv b/rtl/ibex/lowrisc_prim/prim_esc_receiver.sv
@@ -16,7 +16,7 @@
 //
 // See also: prim_esc_sender, prim_diff_decode, alert_handler
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module prim_esc_receiver
   import prim_esc_pkg::*;

diff --git a/rtl/ibex/lowrisc_prim/prim_esc_sender.sv b/rtl/ibex/lowrisc_prim/prim_esc_sender.sv
@@ -19,7 +19,7 @@
 //
 // See also: prim_esc_receiver, prim_diff_decode, alert_handler
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module prim_esc_sender
   import prim_esc_pkg::*;

diff --git a/rtl/ibex/lowrisc_prim/prim_fifo_async.sv b/rtl/ibex/lowrisc_prim/prim_fifo_async.sv
@@ -4,7 +4,7 @@
 //
 // Generic asynchronous fifo for use in a variety of devices.
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module prim_fifo_async #(
   parameter  int unsigned Width  = 16,

diff --git a/rtl/ibex/lowrisc_prim/prim_fifo_sync.sv b/rtl/ibex/lowrisc_prim/prim_fifo_sync.sv
@@ -4,7 +4,7 @@
 //
 // Generic synchronous fifo for use in a variety of devices.
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module prim_fifo_sync #(
   parameter int unsigned Width       = 16,

diff --git a/rtl/ibex/lowrisc_prim/prim_gate_gen.sv b/rtl/ibex/lowrisc_prim/prim_gate_gen.sv
@@ -31,7 +31,7 @@
 // If valid_i constantly set to 1'b1, the gate generator produces around 2.5% smaller designs for
 // the configurations listed in the table above.
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 module prim_gate_gen #(
   parameter int DataWidth = 32,
   parameter int NumGates = 1000

diff --git a/rtl/ibex/lowrisc_prim/prim_gf_mult.sv b/rtl/ibex/lowrisc_prim/prim_gf_mult.sv
@@ -24,7 +24,7 @@
 // https://ieeexplore.ieee.org/document/542803
 
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module prim_gf_mult #(
   parameter int Width = 32,

diff --git a/rtl/ibex/lowrisc_prim/prim_keccak.sv b/rtl/ibex/lowrisc_prim/prim_keccak.sv
@@ -3,7 +3,7 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 // prim_keccak is single round permutation module
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 module prim_keccak #(
   parameter int Width = 1600, // b= {25, 50, 100, 200, 400, 800, 1600}
 

diff --git a/rtl/ibex/lowrisc_prim/prim_lc_sender.sv b/rtl/ibex/lowrisc_prim/prim_lc_sender.sv
@@ -8,7 +8,7 @@
 // for each bit in the life cycle control signal such that tools do not
 // optimize the multibit encoding.
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module prim_lc_sender (
   input                       clk_i,

diff --git a/rtl/ibex/lowrisc_prim/prim_lc_sync.sv b/rtl/ibex/lowrisc_prim/prim_lc_sync.sv
@@ -8,7 +8,7 @@
 // Should be used exactly as recommended in the life cycle controller spec:
 // https://docs.opentitan.org/hw/ip/lc_ctrl/doc/index.html#control-signal-propagation
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module prim_lc_sync #(
   // Number of separately buffered output signals.

diff --git a/rtl/ibex/lowrisc_prim/prim_lfsr.sv b/rtl/ibex/lowrisc_prim/prim_lfsr.sv
@@ -24,7 +24,7 @@
 //       [2] https://users.ece.cmu.edu/~koopman/lfsr/
 //       [3] https://www.xilinx.com/support/documentation/application_notes/xapp052.pdf
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module prim_lfsr #(
   // Lfsr Type, can be FIB_XNOR or GAL_XOR

diff --git a/rtl/ibex/lowrisc_prim/prim_multibit_sync.sv b/rtl/ibex/lowrisc_prim/prim_multibit_sync.sv
@@ -35,7 +35,7 @@
 // Note: CDC tools will likely flag this module due to re-convergent logic.
 //
 
-`include "prim_assert.sv"
+`include "prim_assert.svh"
 
 module prim_multibit_sync #(
   // Width of the multibit signal.