Skip to content

Commit

Permalink
AXI-RT: Update to newest version, add simple example
Browse files Browse the repository at this point in the history
  • Loading branch information
@thommythomaso @alex96295
thommythomaso authored and alex96295 committed Sep 15, 2023
1 parent ae97aca commit e7af6b4
Show file tree
Hide file tree
Showing 15 changed files with 613 additions and 13,170 deletions.
13 changes: 11 additions & 2 deletions Bender.lock
View file
Original file line number Diff line number Diff line change
Expand Up @@ -43,6 +43,15 @@ packages:
- axi
- common_cells
- common_verification
axi_rt:
revision: 7a00678deb73000890acbc7b35a85858bbf2e289
version: null
source:
Git: https://github.com/pulp-platform/axi_rt.git
dependencies:
- axi
- common_cells
- register_interface
axi_vga:
revision: 07be187d1e954d8090031b32d236ad76dc62ce45
version: 0.1.1
Expand Down Expand Up @@ -136,8 +145,8 @@ packages:
- register_interface
- tech_cells_generic
register_interface:
revision: 3b2bf592100b769977c76e51812c55cd742882f6
version: 0.4.1
revision: aa725095a2c67992e07a9be136cfb1ef3f471c1e
version: null
source:
Git: https://github.com/pulp-platform/register_interface.git
dependencies:
Expand Down
6 changes: 2 additions & 4 deletions Bender.yml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,14 +16,15 @@ dependencies:
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0 }
axi_llc: { git: "https://github.com/pulp-platform/axi_llc.git", version: 0.2.1 }
axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.8.1 }
axi_rt: { git: "https://github.com/pulp-platform/axi_rt.git", rev: bus_guard-tbenz }
axi_vga: { git: "https://github.com/pulp-platform/axi_vga.git", version: 0.1.1 }
clint: { git: "https://github.com/pulp-platform/clint.git", version: 0.2.0 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 }
common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 }
cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: pulp-v0.4.3 }
iDMA: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.5.0 }
opentitan_peripherals: { git: "https://github.com/pulp-platform/opentitan_peripherals.git", version: 0.4.0 }
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.1 }
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: aa72509 }
riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.0 }
serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.0 }
clic: { git: "https://github.com/pulp-platform/clic.git", version: 2.0.0 }
Expand All @@ -34,12 +35,9 @@ export_include_dirs:
- hw/include

sources:
- hw/future/axi_to_reg_v2.sv
- hw/bootrom/cheshire_bootrom.sv
- hw/regs/cheshire_reg_pkg.sv
- hw/regs/cheshire_reg_top.sv
- hw/regs/axi_rt_reg_pkg.sv
- hw/regs/axi_rt_reg_top.sv
- hw/cheshire_pkg.sv
- hw/cheshire_soc.sv

Expand Down
16 changes: 10 additions & 6 deletions cheshire.mk
View file
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@ CHS_LLC_DIR := $(shell $(BENDER) path axi_llc)
# Define paths used in dependencies
OTPROOT := $(shell $(BENDER) path opentitan_peripherals)
CLINTROOT := $(shell $(BENDER) path clint)
AXIRTROOT := $(shell $(BENDER) path axi_rt)
AXI_VGA_ROOT := $(shell $(BENDER) path axi_vga)
IDMA_ROOT := $(shell $(BENDER) path idma)

Expand Down Expand Up @@ -74,10 +75,6 @@ include $(CHS_ROOT)/sw/sw.mk
$(CHS_ROOT)/hw/regs/cheshire_reg_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_reg_top.sv: $(CHS_ROOT)/hw/regs/cheshire_regs.hjson
$(REGTOOL) -r $< --outdir $(dir $@)

# AXI RT registers
$(CHS_ROOT)/hw/regs/axi_rt_reg_pkg.sv $(CHS_ROOT)/hw/regs/axi_rt_reg_top.sv: $(CHS_ROOT)/hw/regs/axi_rt_regs.hjson
$(REGTOOL) -r $< --outdir $(dir $@)

# CLINT
CLINTCORES ?= 1
include $(CLINTROOT)/clint.mk
Expand All @@ -89,6 +86,13 @@ include $(OTPROOT)/otp.mk
$(OTPROOT)/.generated: $(CHS_ROOT)/hw/rv_plic.cfg.hjson
flock -x $@ sh -c "cp $< $(dir $@)/src/rv_plic/; $(MAKE) -j1 otp" && touch $@

# AXI RT
AXIRT_NUM_MGRS ?= 8
AXIRT_NUM_SUBS ?= 2
include $(AXIRTROOT)/axirt.mk
$(AXIRTROOT)/.generated: axirt_regs
touch $@

# AXI VGA
include $(AXI_VGA_ROOT)/axi_vga.mk
$(AXI_VGA_ROOT)/.generated:
Expand All @@ -100,9 +104,9 @@ $(CHS_SLINK_DIR)/.generated: $(CHS_ROOT)/hw/serial_link.hjson
flock -x $@ $(MAKE) -C $(CHS_SLINK_DIR) update-regs && touch $@

CHS_HW_ALL += $(CHS_ROOT)/hw/regs/cheshire_reg_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_reg_top.sv
CHS_HW_ALL += $(CHS_ROOT)/hw/regs/axi_rt_reg_pkg.sv $(CHS_ROOT)/hw/regs/axi_rt_reg_top.sv
CHS_HW_ALL += $(CLINTROOT)/.generated
CHS_HW_ALL += $(OTPROOT)/.generated
CHS_HW_ALL += $(AXIRTROOT)/.generated
CHS_HW_ALL += $(AXI_VGA_ROOT)/.generated
CHS_HW_ALL += $(CHS_SLINK_DIR)/.generated

Expand All @@ -129,7 +133,7 @@ CHS_BOOTROM_ALL += $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.sv $(CHS_ROOT)/hw/boo
##############

$(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl: Bender.yml
$(BENDER) script vsim -t sim -t cv64a6_imafdcsclic_sv39 -t test -t cva6 --vlog-arg="$(VLOG_ARGS)" > $@
$(BENDER) script vsim -t sim -t cv64a6_imafdcsclic_sv39 -t test -t cva6 -t rtl --vlog-arg="$(VLOG_ARGS)" > $@
echo 'vlog "$(CURDIR)/$(CHS_ROOT)/target/sim/src/elfloader.cpp" -ccflags "-std=c++11"' >> $@

$(CHS_ROOT)/target/sim/models:
Expand Down
6 changes: 3 additions & 3 deletions docs/um/arch.md
View file
Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,8 @@ Cheshire's internal memory map is *static*. While device instantiation and layou
| | CLINT | `0x0204_0000` | 256K | |
| +-------------------+---------------+------+-------+
| | IRQ router | `0x0208_0000` | 256K | |
| +-------------------+---------------+------+-------+
| | AXI RT (Cfg) | `0x020C_0000` | 256K | |
+--------------------+-------------------+---------------+------+-------+
| 4K periphs @ Reg | SoC Regs | `0x0300_0000` | 4K | |
| +-------------------+---------------+------+-------+
Expand All @@ -58,9 +60,7 @@ Cheshire's internal memory map is *static*. While device instantiation and layou
| +-------------------+---------------+------+-------+
| | VGA (Cfg) | `0x0300_7000` | 4K | |
| +-------------------+---------------+------+-------+
| | AXI RT (Cfg) | `0x0300_8000` | 4K | |
| +-------------------+---------------+------+-------+
| | UNBENT | `0x0300_9000` | 4K | |
| | UNBENT | `0x0300_8000` | 4K | |
+--------------------+-------------------+---------------+------+-------+
| INTCs @ Reg | PLIC | `0x0400_0000` | 64M | |
| +-------------------+---------------+------+-------+
Expand Down
18 changes: 11 additions & 7 deletions hw/cheshire_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -180,8 +180,10 @@ package cheshire_pkg;
// Parameters for GPIO
bit GpioInputSyncs;
// Parameters for AXI RT
word_bt AxiRtNumPending;
word_bt AxiRtWBufferDepth;
aw_bt AxiRtNumPending;
dw_bt AxiRtWBufferDepth;
aw_bt AxiRtNumAddrRegions;
bit AxiRtCutPaths;
} cheshire_cfg_t;

//////////////////
Expand Down Expand Up @@ -263,7 +265,7 @@ package cheshire_pkg;
localparam doub_bt AmRegs = 'h0300_0000;
localparam doub_bt AmLlc = 'h0300_1000;
localparam doub_bt AmSlink = 'h0300_6000;
localparam doub_bt AmBusErr = 'h0300_9000;
localparam doub_bt AmBusErr = 'h0300_8000;
localparam doub_bt AmSpm = 'h1000_0000; // Cached region at bottom, uncached on top
localparam doub_bt AmClic = 'h0800_0000;

Expand Down Expand Up @@ -400,8 +402,8 @@ package cheshire_pkg;
if (cfg.Gpio) begin i++; ret.gpio = i; r++; ret.map[r] = '{i, 'h0300_5000, 'h0300_6000}; end
if (cfg.SerialLink) begin i++; ret.slink = i; r++; ret.map[r] = '{i, AmSlink, AmSlink +'h1000}; end
if (cfg.Vga) begin i++; ret.vga = i; r++; ret.map[r] = '{i, 'h0300_7000, 'h0300_8000}; end
if (cfg.AxiRt) begin i++; ret.axirt = i; r++; ret.map[r] = '{i, 'h0300_8000, 'h0300_9000}; end
if (cfg.IrqRouter) begin i++; ret.irq_router = i; r++; ret.map[r] = '{i, 'h0208_0000, 'h020c_0000}; end
if (cfg.AxiRt) begin i++; ret.axirt = i; r++; ret.map[r] = '{i, 'h020c_0000, 'h0210_0000}; end
if (cfg.Clic) for (int j = 0; j < cfg.NumCores; j++) begin
i++; ret.clic[j] = i; r++; ret.map[r] = '{i, AmClic + j*'h40000, AmClic + (j+1)*'h40000};
end
Expand Down Expand Up @@ -539,7 +541,7 @@ package cheshire_pkg;
Dma : 1,
SerialLink : 1,
Vga : 1,
AxiRt : 0,
AxiRt : 1,
Clic : 0,
IrqRouter : 0,
BusErr : 1,
Expand Down Expand Up @@ -590,8 +592,10 @@ package cheshire_pkg;
// GPIOs
GpioInputSyncs : 1,
// AXI RT
AxiRtNumPending : 16,
AxiRtWBufferDepth : 16,
AxiRtNumPending : 16,
AxiRtWBufferDepth : 16,
AxiRtNumAddrRegions : 2,
AxiRtCutPaths : 1,
// All non-set values should be zero
default: '0
};
Expand Down
103 changes: 31 additions & 72 deletions hw/cheshire_soc.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1095,86 +1095,45 @@ module cheshire_soc import cheshire_pkg::*; #(

if (Cfg.AxiRt) begin : gen_axi_rt

// Connect AXI RT units, one for each master
axi_rt_reg_pkg::axi_rt_hw2reg_t axi_rt_hw2reg;
axi_rt_reg_pkg::axi_rt_reg2hw_t axi_rt_reg2hw;

// Rule type
typedef struct packed {
logic [0:0] idx;
addr_t start_addr;
addr_t end_addr;
} rt_rule_t;

localparam rt_rule_t [0:0] RtAddrmap = '{
'{ idx: 8'h00, start_addr: '0, end_addr: '1 }
};

for (genvar i = 0; i < AxiIn.num_in; i++) begin : gen_axi_rt_units
axi_rt_unit #(
.AddrWidth ( Cfg.AddrWidth ),
.DataWidth ( Cfg.AxiDataWidth ),
.IdWidth ( Cfg.AxiMstIdWidth ),
.UserWidth ( Cfg.AxiUserWidth ),
.NumPending ( Cfg.AxiRtNumPending ),
.WBufferDepth ( Cfg.AxiRtWBufferDepth ),
.NumAddrRegions ( 1 ),
.NumRules ( 1 ),
.PeriodWidth ( 32 ),
.BudgetWidth ( 32 ),
.rt_rule_t ( rt_rule_t ),
.addr_t ( addr_t ),
.aw_chan_t ( axi_mst_aw_chan_t ),
.w_chan_t ( axi_mst_w_chan_t ),
.axi_req_t ( axi_mst_req_t ),
.axi_resp_t ( axi_mst_rsp_t )
) i_axi_rt_unit (
.clk_i,
.rst_ni,
.slv_req_i ( axi_in_req [i] ),
.slv_resp_o ( axi_in_rsp [i] ),
.mst_req_o ( axi_rt_in_req [i] ),
.mst_resp_i ( axi_rt_in_rsp [i] ),
.rt_enable_i ( axi_rt_reg2hw.rt_enable [i] ),
.rt_bypassed_o ( axi_rt_hw2reg.rt_bypassed [i] ),
.len_limit_i ( axi_rt_reg2hw.len_limit [i] ),
.num_w_pending_o ( ),
.num_aw_pending_o ( ),
.rt_rule_i ( RtAddrmap ),
.w_decode_error_o ( ),
.r_decode_error_o ( ),
.imtu_enable_i ( axi_rt_reg2hw.imtu_enable [i] ),
.imtu_abort_i ( axi_rt_reg2hw.imtu_abort [i] ),
.w_budget_i ( axi_rt_reg2hw.write_budget [i] ),
.w_budget_left_o ( axi_rt_hw2reg.write_budget_left [i] ),
.w_period_i ( axi_rt_reg2hw.write_period [i] ),
.w_period_left_o ( axi_rt_hw2reg.write_period_left [i] ),
.r_budget_i ( axi_rt_reg2hw.read_budget [i] ),
.r_budget_left_o ( axi_rt_hw2reg.read_budget_left [i] ),
.r_period_i ( axi_rt_reg2hw.read_period [i] ),
.r_period_left_o ( axi_rt_hw2reg.read_period_left [i] ),
.isolate_o ( axi_rt_hw2reg.isolate [i] ),
.isolated_o ( axi_rt_hw2reg.isolated [i] )
);
end

axi_rt_reg_top #(
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t )
) i_axi_rt_regs (
axi_rt_unit_top #(
.NumManagers ( AxiIn.num_in ),
.AddrWidth ( Cfg.AddrWidth ),
.DataWidth ( Cfg.AxiDataWidth ),
.IdWidth ( Cfg.AxiMstIdWidth ),
.UserWidth ( Cfg.AxiUserWidth ),
.NumPending ( Cfg.AxiRtNumPending ),
.WBufferDepth ( Cfg.AxiRtWBufferDepth ),
.NumAddrRegions ( Cfg.AxiRtNumAddrRegions ),
.PeriodWidth ( 32'd32 ),
.BudgetWidth ( 32'd32 ),
.RegIdWidth ( AxiSlvIdWidth ),
.CutSplitterPaths ( Cfg.AxiRtCutPaths ),
.CutDecErrors ( 1'b0 ),
.aw_chan_t ( axi_mst_aw_chan_t ),
.w_chan_t ( axi_mst_w_chan_t ),
.b_chan_t ( axi_mst_b_chan_t ),
.ar_chan_t ( axi_mst_ar_chan_t ),
.r_chan_t ( axi_mst_r_chan_t ),
.axi_req_t ( axi_mst_req_t ),
.axi_resp_t ( axi_mst_rsp_t ),
.req_req_t ( reg_req_t ),
.req_rsp_t ( reg_rsp_t )
) i_axi_rt_unit_top (
.clk_i,
.rst_ni,
.slv_req_i ( axi_in_req ),
.slv_resp_o ( axi_in_rsp ),
.mst_req_o ( axi_rt_in_req ),
.mst_resp_i ( axi_rt_in_rsp ),
.reg_req_i ( reg_out_req[RegOut.axirt] ),
.reg_rsp_o ( reg_out_rsp[RegOut.axirt] ),
.hw2reg ( axi_rt_hw2reg ),
.reg2hw ( axi_rt_reg2hw ),
.devmode_i ( 1'b1 )
.reg_id_i ( reg_id )
);

end else begin : gen_no_axi_rt

assign axi_rt_in_req = axi_in_req;
assign axi_in_rsp = axi_rt_in_rsp;
assign axi_rt_in_req = axi_in_req;
assign axi_in_rsp = axi_rt_in_rsp;

end

Expand Down
Loading

0 comments on commit e7af6b4

Please sign in to comment.