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WIP: Connect DMA using regbus
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@thommythomaso
thommythomaso committed Nov 29, 2024
1 parent 97fddf4 commit 830b1e6
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Showing 4 changed files with 19 additions and 87 deletions.
48 changes: 12 additions & 36 deletions hw/cheshire_idma_wrap.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,16 +21,16 @@ module cheshire_idma_wrap #(
parameter bit IsTwoD = 0,
parameter type axi_mst_req_t = logic,
parameter type axi_mst_rsp_t = logic,
parameter type axi_slv_req_t = logic,
parameter type axi_slv_rsp_t = logic
parameter type reg_req_t = logic,
parameter type reg_rsp_t = logic
) (
input logic clk_i,
input logic rst_ni,
input logic testmode_i,
output axi_mst_req_t axi_mst_req_o,
input axi_mst_rsp_t axi_mst_rsp_i,
input axi_slv_req_t axi_slv_req_i,
output axi_slv_rsp_t axi_slv_rsp_o
input reg_req_t reg_req_i,
output reg_rsp_t reg_rsp_o
);

`include "axi/assign.svh"
Expand Down Expand Up @@ -63,8 +63,6 @@ module cheshire_idma_wrap #(
`IDMA_TYPEDEF_FULL_RSP_T(idma_rsp_t, addr_t)
`IDMA_TYPEDEF_FULL_ND_REQ_T(idma_nd_req_t, idma_req_t, tf_len_t, tf_len_t)

`REG_BUS_TYPEDEF_ALL(dma_regs, addr_t, data_t, strb_t)

typedef struct packed {
axi_ar_chan_t ar_chan;
} axi_read_meta_channel_t;
Expand All @@ -81,9 +79,6 @@ module cheshire_idma_wrap #(
axi_write_meta_channel_t axi;
} write_meta_channel_t;

dma_regs_req_t dma_reg_req;
dma_regs_rsp_t dma_reg_rsp;

// 1D FE signals
idma_req_t burst_req_d;
logic be_valid_d;
Expand Down Expand Up @@ -122,39 +117,20 @@ module cheshire_idma_wrap #(
axi_mst_req_t axi_read_req, axi_write_req;
axi_mst_rsp_t axi_read_rsp, axi_write_rsp;

axi_to_reg #(
.ADDR_WIDTH ( AxiAddrWidth ),
.DATA_WIDTH ( AxiDataWidth ),
.ID_WIDTH ( AxiSlvIdWidth ),
.USER_WIDTH ( AxiUserWidth ),
.axi_req_t ( axi_slv_req_t ),
.axi_rsp_t ( axi_slv_rsp_t ),
.reg_req_t ( dma_regs_req_t ),
.reg_rsp_t ( dma_regs_rsp_t )
) i_axi_translate (
.clk_i,
.rst_ni,
.testmode_i,
.axi_req_i ( axi_slv_req_i ),
.axi_rsp_o ( axi_slv_rsp_o ),
.reg_req_o ( dma_reg_req ),
.reg_rsp_i ( dma_reg_rsp )
);

if (!IsTwoD) begin : gen_1d

idma_reg64_1d #(
.NumRegs ( 32'd1 ),
.NumStreams ( 32'd1 ),
.IdCounterWidth ( IdCounterWidth ),
.reg_req_t ( dma_regs_req_t ),
.reg_rsp_t ( dma_regs_rsp_t ),
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t ),
.dma_req_t ( idma_req_t )
) i_dma_frontend_1d (
.clk_i,
.rst_ni,
.dma_ctrl_req_i ( dma_reg_req ),
.dma_ctrl_rsp_o ( dma_reg_rsp ),
.dma_ctrl_req_i ( reg_req_i ),
.dma_ctrl_rsp_o ( reg_rsp_o ),
.dma_req_o ( burst_req_d ),
.req_valid_o ( be_valid_d ),
.req_ready_i ( be_ready_d ),
Expand Down Expand Up @@ -203,14 +179,14 @@ module cheshire_idma_wrap #(
.NumRegs ( 1 ),
.NumStreams ( 1 ),
.IdCounterWidth ( IdCounterWidth ),
.reg_req_t ( dma_regs_req_t ),
.reg_rsp_t ( dma_regs_rsp_t ),
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t ),
.dma_req_t ( idma_nd_req_t )
) idma_frontend_2d (
.clk_i,
.rst_ni,
.dma_ctrl_req_i ( dma_reg_req ),
.dma_ctrl_rsp_o ( dma_reg_rsp ),
.dma_ctrl_req_i ( reg_req_i ),
.dma_ctrl_rsp_o ( reg_rsp_o ),
.dma_req_o ( idma_nd_req_d ),
.req_valid_o ( idma_nd_req_valid_d ),
.req_ready_i ( idma_nd_req_ready_d ),
Expand Down
4 changes: 2 additions & 2 deletions hw/cheshire_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -331,7 +331,6 @@ package cheshire_pkg;
aw_bt reg_demux;
aw_bt llc;
aw_bt spm;
aw_bt dma;
aw_bt slink;
aw_bt ext_base;
aw_bt num_out;
Expand All @@ -357,7 +356,6 @@ package cheshire_pkg;
r++; ret.map[r] = '{i, AmSpm, AmSpm + SizeSpm};
r++; ret.map[r] = '{i, AmSpm + 'h0400_0000, AmSpm + 'h0400_0000 + SizeSpm};
end
if (cfg.Dma) begin i++; r++; ret.dma = i; ret.map[r] = '{i, 'h0100_0000, 'h0100_1000}; end
if (cfg.SerialLink) begin i++; r++; ret.slink = i;
ret.map[r] = '{i, cfg.SlinkRegionStart, cfg.SlinkRegionEnd}; end
// External port indices start after internal ones
Expand Down Expand Up @@ -394,6 +392,7 @@ package cheshire_pkg;
aw_bt slink;
aw_bt vga;
aw_bt usb;
aw_bt dma;
aw_bt axirt;
aw_bt irq_router;
aw_bt [2**MaxCoresWidth-1:0] bus_err;
Expand All @@ -419,6 +418,7 @@ package cheshire_pkg;
if (cfg.SerialLink) begin i++; ret.slink = i; r++; ret.map[r] = '{i, AmSlink, AmSlink +'h1000}; end
if (cfg.Vga) begin i++; ret.vga = i; r++; ret.map[r] = '{i, 'h0300_7000, 'h0300_8000}; end
if (cfg.Usb) begin i++; ret.usb = i; r++; ret.map[r] = '{i, 'h0300_8000, 'h0300_9000}; end
if (cfg.Dma) begin i++; ret.dma = i; r++; ret.map[r] = '{i, 'h0300_b000, 'h0300_c000}; end
if (cfg.IrqRouter) begin i++; ret.irq_router = i; r++; ret.map[r] = '{i, 'h0208_0000, 'h020c_0000}; end
if (cfg.AxiRt) begin i++; ret.axirt = i; r++; ret.map[r] = '{i, 'h020c_0000, 'h0210_0000}; end
if (cfg.Clic) for (int j = 0; j < cfg.NumCores; j++) begin
Expand Down
52 changes: 4 additions & 48 deletions hw/cheshire_soc.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1369,50 +1369,6 @@ module cheshire_soc import cheshire_pkg::*; #(

if (Cfg.Dma) begin : gen_dma

axi_slv_req_t dma_amo_req, dma_cut_req;
axi_slv_rsp_t dma_amo_rsp, dma_cut_rsp;

axi_riscv_atomics_structs #(
.AxiAddrWidth ( Cfg.AddrWidth ),
.AxiDataWidth ( Cfg.AxiDataWidth ),
.AxiIdWidth ( AxiSlvIdWidth ),
.AxiUserWidth ( Cfg.AxiUserWidth ),
.AxiMaxReadTxns ( Cfg.DmaConfMaxReadTxns ),
.AxiMaxWriteTxns ( Cfg.DmaConfMaxWriteTxns ),
.AxiUserAsId ( 1 ),
.AxiUserIdMsb ( Cfg.AxiUserAmoMsb ),
.AxiUserIdLsb ( Cfg.AxiUserAmoLsb ),
.RiscvWordWidth ( 64 ),
.NAxiCuts ( Cfg.DmaConfAmoNumCuts ),
.axi_req_t ( axi_slv_req_t ),
.axi_rsp_t ( axi_slv_rsp_t )
) i_dma_conf_atomics (
.clk_i,
.rst_ni,
.axi_slv_req_i ( axi_out_req[AxiOut.dma] ),
.axi_slv_rsp_o ( axi_out_rsp[AxiOut.dma] ),
.axi_mst_req_o ( dma_amo_req ),
.axi_mst_rsp_i ( dma_amo_rsp )
);

axi_cut #(
.Bypass ( ~Cfg.DmaConfAmoPostCut ),
.aw_chan_t ( axi_slv_aw_chan_t ),
.w_chan_t ( axi_slv_w_chan_t ),
.b_chan_t ( axi_slv_b_chan_t ),
.ar_chan_t ( axi_slv_ar_chan_t ),
.r_chan_t ( axi_slv_r_chan_t ),
.axi_req_t ( axi_slv_req_t ),
.axi_resp_t ( axi_slv_rsp_t )
) i_dma_conf_atomics_cut (
.clk_i,
.rst_ni,
.slv_req_i ( dma_amo_req ),
.slv_resp_o ( dma_amo_rsp ),
.mst_req_o ( dma_cut_req ),
.mst_resp_i ( dma_cut_rsp )
);

axi_mst_req_t axi_dma_req;

always_comb begin
Expand All @@ -1435,16 +1391,16 @@ module cheshire_soc import cheshire_pkg::*; #(
.IsTwoD ( Cfg.DmaConfEnableTwoD ),
.axi_mst_req_t ( axi_mst_req_t ),
.axi_mst_rsp_t ( axi_mst_rsp_t ),
.axi_slv_req_t ( axi_slv_req_t ),
.axi_slv_rsp_t ( axi_slv_rsp_t )
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t )
) i_idma (
.clk_i,
.rst_ni,
.testmode_i ( test_mode_i ),
.axi_mst_req_o ( axi_dma_req ),
.axi_mst_rsp_i ( axi_in_rsp[AxiIn.dma] ),
.axi_slv_req_i ( dma_cut_req ),
.axi_slv_rsp_o ( dma_cut_rsp )
.reg_req_i ( reg_out_req[RegOut.dma] ),
.reg_rsp_o ( reg_out_rsp[RegOut.dma] )
);

if (Cfg.BusErr) begin : gen_dma_bus_err
Expand Down
2 changes: 1 addition & 1 deletion sw/link/common.ldh
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ SECTIONS {
__stack_pointer$ = 0;

/* Further addresses */
__base_dma = 0x01000000;
__base_dma = 0x0300b000;
__base_bootrom = 0x02000000;
__base_clint = 0x02040000;
__base_axirt = 0x020C0000;
Expand Down

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