WIP: Signal and instantiation cleanup

hw/newusb/new_usb_dmaoutputqueueED.sv

@@ -102,12 +102,14 @@ module new_usb_dmaoutputqueueED import new_usb_dmaoutputqueueED_pkg::*; #(
     assign en = dma_handshake && ~dma_handshake_prev;
 
     // secondin registers
+    // Todo: replace with register chain
     `FFL(dword0, dma_data_i, en, 32b'0) // Dword0
     `FFL(dword1, dword0,   en, 32b'0) // Dword1
     `FFL(dword2, dword1,   en, 32b'0) // Dword2
     `FFL(dword3, dword2,   en, 32b'0) // Dword3
 
     // secondin fill propagation
+    // Todo: replace with register chain
     logic propagate_level0;
     logic propagate_level1;
     logic propagate_level2;
@@ -136,7 +138,7 @@ module new_usb_dmaoutputqueueED import new_usb_dmaoutputqueueED_pkg::*; #(
     // stash and secondin muxed into firstin
     assign secondinmux = non_empty_context_switch_p2np ? stash : secondin;
 
-    // The nextED address needs to be updated in firstin in case secondinED has no TD and the next ED is loaded instead.
+    // The nextED address needs to be updated in firstin in case secondinED has no TD and secondin's nextED is loaded instead.
     assign firstin_nextED_overwrite = pop_i || empty_secondin_o;
     `FFL(firstin.status.MPS,     secondinmux.status.MPS,     pop_i, '0) // firstin register
     `FFL(firstin.status.F,       secondinmux.status.F,       pop_i, '0) // firstin register

hw/newusb/new_usb_listservice.sv

@@ -17,48 +17,47 @@
 // if interrupt done do periodic_frame 0
 
 module new_usb_listservice import new_usb_ohci_pkg::*; (
-
+
+  /// control
   input logic clk_i,
   input logic rst_ni,
+  input  logic          start_i, // start list service
+  input  logic          frame_periodic_i, // frame is currently in periodic or nonperiodic zone
+  input  logic          counter_is_threshold_i, // nonperiodic counter full, switch to bulk
 
-  input  logic          frame_periodic, // frame is currently in periodic or nonperiodic zone
-  input  logic          frame_request,  // frame requests new data
-
-  //next ED or TD and one of the four channel types
+  /// next ED or TD and one of the four channel types
   input  logic          nextis_valid_i // needs to be one clock cycle
   input  logic          nextis_ed_i,
   input  channel        nextis_type_i,
   input  logic   [27:0] nextis_address_i,
   output logic          nextis_ready_o, // listservice is ready for nextis
-
-  input  logic          counter_is_threshold_i, // nonperiodic counter full, switch to bulk
 
-  output logic          controlbulkratio_qe,
+  /// registers
   input  logic   [ 1:0] controlbulkratio_q,
 
-  output logic          periodcurrent_ed_de,
-  output logic   [27:0] periodcurrent_ed_d,
-  input  logic   [27:0] periodcurrent_ed_q,
+  output logic          periodcurrent_ed_de_o,
+  output logic   [27:0] periodcurrent_ed_d_o,
+  input  logic   [27:0] periodcurrent_ed_q_i,
 
-  output logic          controlcurrent_ed_de,
-  output logic   [27:0] controlcurrent_ed_d,
-  input  logic   [27:0] controlcurrent_ed_q,
+  output logic          controlcurrent_ed_de_o,
+  output logic   [27:0] controlcurrent_ed_d_o,
+  input  logic   [27:0] controlcurrent_ed_q_i,
 
-  output logic          bulkcurrent_ed_de,
-  output logic   [27:0] bulkcurrent_ed_d,
-  input  logic   [27:0] bulkcurrent_ed_q,
+  output logic          bulkcurrent_ed_de_o,
+  output logic   [27:0] bulkcurrent_ed_d_o,
+  input  logic   [27:0] bulkcurrent_ed_q_i,
 
-  output logic          hcbulkhead_ed_de,
-  output logic   [27:0] hcbulkhead_ed_d,
-  input  logic   [27:0] hcbulkhead_ed_q,
+  output logic          hcbulkhead_ed_de_o,
+  output logic   [27:0] hcbulkhead_ed_d_o,
+  input  logic   [27:0] hcbulkhead_ed_q_i,
 
-  output logic          controlhead_ed_de,
-  output logic   [27:0] controlhead_ed_d,
-  input  logic   [27:0] controlhead_ed_q,
+  output logic          controlhead_ed_de_o,
+  output logic   [27:0] controlhead_ed_d_o,
+  input  logic   [27:0] controlhead_ed_q_i,
 
+  /// send
   output logic   [27:0] nextreadwriteaddress_o,
   output logic          validdmaaccess_o,
-  output logic          dmawriteorread_o, // write high, read low
   output channel        current_type_o,
   output logic          current_ed_o,
 

hw/newusb/new_usb_ohci.sv

@@ -123,45 +123,40 @@ module new_usb_ohci import new_usb_ohci_pkg::*; #(
   logic [27:0] nextis_address;
 
   new_usb_listservice i_listservice (
-
+    /// control
     .clk_i(soc_clk_i),
-    .rst_i(soc_rst_ni),
-
-    .start(start),
-    .frame_periodic(frame_periodic),
-
-    .nextis_valid(nextis_valid),
-    .nextis_ed(nextis_ed),
-    .nextis_type(nextis_type),
-    .nextis_address(nextis_address),
-
+    .rst_ni(soc_rst_ni),
+    .start_i(start),
+    .frame_periodic_i(frame_periodic),
+    .counter_is_threshold_i(counter_is_threshold),
+    /// next ED or TD and one of the four channel types
+    .nextis_valid_i(nextis_valid),
+    .nextis_ed_i(nextis_ed),
+    .nextis_type_i(nextis_type),
+    .nextis_address_i(nextis_address),
+    .nextis_ready_o(nextis_ready),
+    /// registers
     .controlbulkratio_q(reg2hw.hccontrol.cbsr.q),
-
-    .periodcurrent_ed_de(newusb_hw2reg.hcperiodcurrented.pced.de),
-    .periodcurrent_ed_d(newusb_hw2reg.hcperiodcurrented.pced.d),
-    .periodcurrent_ed_q(newusb_reg2hw.hcperiodcurrented.pced.q),
-
-    .controlcurrent_ed_de(newusb_hw2reg.hccontrolcurrented.cced.de),
-    .controlcurrent_ed_d(newusb_hw2reg.hccontrolcurrented.cced.d),
-    .controlcurrent_ed_q(newusb_reg2hw.hccontrolcurrented.cced.q),
-
-    .bulkcurrent_ed_de(newusb_hw2reg.hcbulkcurrented.bced.de),
-    .bulkcurrent_ed_d(newusb_hw2reg.hcbulkcurrented.bced.d),
-    .bulkcurrent_ed_q(newusb_reg2hw.hcbulkcurrented.bced.q),
-
-    .hcbulkhead_ed_de(newusb_hw2reg.hcbulkheaded.bhed.de),
-    .hcbulkhead_ed_d(newusb_hw2reg.hcbulkheaded.bhed.d) ,
-    .hcbulkhead_ed_q(newusb_reg2hw.hcbulkheaded.bhed.q),
-
-    .controlhead_ed_de(newusb_hw2reg.hccontrolheaded.ched.de),
-    .controlhead_ed_d(newusb_hw2reg.hccontrolheaded.ched.d) ,
-    .controlhead_ed_q(newusb_reg2hw.hccontrolheaded.ched.q),
-
-    .nextreadwriteaddress(),
-    .validdmaaccess(),
-    .current_type(),
-    .sent_head()
-
+    .periodcurrent_ed_de_o(newusb_hw2reg.hcperiodcurrented.pced.de),
+    .periodcurrent_ed_d_o(newusb_hw2reg.hcperiodcurrented.pced.d),
+    .periodcurrent_ed_q_i(newusb_reg2hw.hcperiodcurrented.pced.q),
+    .controlcurrent_ed_de_o(newusb_hw2reg.hccontrolcurrented.cced.de),
+    .controlcurrent_ed_d_o(newusb_hw2reg.hccontrolcurrented.cced.d),
+    .controlcurrent_ed_q_i(newusb_reg2hw.hccontrolcurrented.cced.q),
+    .bulkcurrent_ed_de_o(newusb_hw2reg.hcbulkcurrented.bced.de),
+    .bulkcurrent_ed_d_o(newusb_hw2reg.hcbulkcurrented.bced.d),
+    .bulkcurrent_ed_q_i(newusb_reg2hw.hcbulkcurrented.bced.q),
+    .hcbulkhead_ed_de_o(newusb_hw2reg.hcbulkheaded.bhed.de),
+    .hcbulkhead_ed_d_o(newusb_hw2reg.hcbulkheaded.bhed.d) ,
+    .hcbulkhead_ed_q_i(newusb_reg2hw.hcbulkheaded.bhed.q),
+    .controlhead_ed_de_o(newusb_hw2reg.hccontrolheaded.ched.de),
+    .controlhead_ed_d_o(newusb_hw2reg.hccontrolheaded.ched.d) ,
+    .controlhead_ed_q_i(newusb_reg2hw.hccontrolheaded.ched.q),
+    /// send
+    .nextreadwriteaddress_o(),
+    .validdmaaccess_o(),
+    .current_type_o(),
+    .sent_head_o()
   );
 
   new_usb_unpackdescriptors #(

hw/newusb/new_usb_registerchain.sv

@@ -24,5 +24,4 @@ module new_usb_registerchain #(
       else       `FFL(register[Width+i-1:i], register[i-1:i-Width], en, '0)
     end
   endgenerate
-
 endmodule

hw/newusb/new_usb_unpackdescriptors.sv

@@ -107,6 +107,7 @@ module new_usb_unpackdescriptors import new_usb_ohci_pkg::*; #(
     assign dma_valid_td    = dma_valid_i && !ed && !dma_flush;
 
     // dma flush, early flush to prevent stage loading, save power and increase speed
+    // Todo: replace with register chain
     logic dma_flush;
     logic dma_flush_en;
     logic flush_level0;