Tagger adjustments:

1. Adjust user Maxpartition and user bits of tagger to be consistent with LLC.
2. Adjust bootrom tagger part correspondingly.
3. Add register compilation in `cheshire.mk` for tagger.
4. Fix a problem of wrong place of tagger module.

Bender.lock

@@ -180,7 +180,7 @@ packages:
     - common_cells
     - register_interface
   tagger:
-    revision: 8df2d026e0ad435ea2761dd2f172771c30520e93
+    revision: 044d92c17728e7c608cd6678d01ec2d749c7ab83
     version: null
     source:
       Git: [email protected]:dishen/tagger.git

Bender.yml

@@ -30,7 +30,7 @@ dependencies:
   clic:                     { git: "https://github.com/pulp-platform/clic.git",                   version: 2.0.0  }
   irq_router:               { git: "https://github.com/pulp-platform/irq_router.git",             rev: d1d3135    }  # TODO: master commit; use next release once out
   bus_err_unit:             { git: "[email protected]:carfield/bus_err_unit.git",            rev: "47a6436"  } # branch: main
-  tagger:                   { git: "[email protected]:dishen/tagger.git",                    rev: 8df2d02    }
+  tagger:                   { git: "[email protected]:dishen/tagger.git",                    rev: 044d92c    }
 
 export_include_dirs:
   - hw/include

cheshire.mk

@@ -20,6 +20,7 @@ CHS_ROOT      ?= $(shell $(BENDER) path cheshire)
 CHS_REG_DIR   := $(shell $(BENDER) path register_interface)
 CHS_SLINK_DIR := $(shell $(BENDER) path serial_link)
 CHS_LLC_DIR   := $(shell $(BENDER) path axi_llc)
+CHS_TAGGER_DIR := $(shell $(BENDER) path tagger)
 
 # Define paths used in dependencies
 OTPROOT      := $(shell $(BENDER) path opentitan_peripherals)
@@ -111,13 +112,19 @@ $(CHS_LLC_DIR)/.generated:
 	$(MAKE) -C $(CHS_LLC_DIR) REGWIDTH=64 CACHENUMLINES=256 MAXPARTITION=$(MAXPARTITION) CACHE_PARTITION=$(CACHE_PARTITION) regs
 	@touch $@
 
+# Tagger configuration
+$(CHS_TAGGER_DIR)/.generated: 
+	$(MAKE) -C $(CHS_TAGGER_DIR) REGWIDTH=32 MAXPARTITION=$(MAXPARTITION) PATID_LEN=5 regs
+	@touch $@
+
 CHS_HW_ALL += $(CHS_ROOT)/hw/regs/cheshire_reg_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_reg_top.sv
 CHS_HW_ALL += $(CLINTROOT)/.generated
 CHS_HW_ALL += $(OTPROOT)/.generated
 CHS_HW_ALL += $(AXIRTROOT)/.generated
 CHS_HW_ALL += $(AXI_VGA_ROOT)/.generated
 CHS_HW_ALL += $(CHS_SLINK_DIR)/.generated
 CHS_HW_ALL += $(CHS_LLC_DIR)/.generated
+CHS_HW_ALL += $(CHS_TAGGER_DIR)/.generated
 
 #####################
 # Generate Boot ROM #

hw/bootrom/cheshire_bootrom.S

@@ -80,13 +80,13 @@ _wait_llc_bist:
     lui t1, 0xFFFFF // 0xFFFF_F000
     sw t1, 4(t0)
 
-    // set patid to 2
-    li t1, 2
-    sw t1, 36(t0)
+    // set patid to 0
+    li t1, 0
+    sw t1, 68(t0)   // 0x44
 
     // set mode to TOR
     li t1, 0x1
-    sw t1, 40(t0)
+    sw t1, 80(t0)   // 0x50
 
     // commit changes
     li t1, 0x1

hw/bootrom/cheshire_bootrom.sv

@@ -63,9 +63,9 @@ module cheshire_bootrom #(
             031: data_o = 32'h6325fe03 /* 0x007c */;
             032: data_o = 32'h737d929a /* 0x0080 */;
             033: data_o = 32'h0062a223 /* 0x0084 */;
-            034: data_o = 32'ha2234309 /* 0x0088 */;
-            035: data_o = 32'h43050262 /* 0x008c */;
-            036: data_o = 32'h0262a423 /* 0x0090 */;
+            034: data_o = 32'ha2234301 /* 0x0088 */;
+            035: data_o = 32'h43050462 /* 0x008c */;
+            036: data_o = 32'h0462a823 /* 0x0090 */;
             037: data_o = 32'ha0234305 /* 0x0094 */;
             038: data_o = 32'h12970062 /* 0x0098 */;
             039: data_o = 32'h82930100 /* 0x009c */;

hw/cheshire_pkg.sv

@@ -494,7 +494,7 @@ package cheshire_pkg;
     // Interconnect
     AddrWidth         : 48,
     AxiDataWidth      : 64,
-    AxiUserWidth      : 10,  // Convention: bit 0 for core(s), bit 1 for serial link TODO: add more bits for llc
+    AxiUserWidth      : 8,  // Convention: bit 0 for core(s), bit 1 for serial link TODO: add more bits for llc
     AxiMstIdWidth     : 2,
     AxiMaxMstTrans    : 8,
     AxiMaxSlvTrans    : 8,

hw/cheshire_soc.sv

@@ -788,17 +788,15 @@ module cheshire_soc import cheshire_pkg::*; #(
       // .mst_req_o  ( axi_in_req[AxiIn.cores[i]] ),
       // .mst_resp_i ( axi_in_rsp[AxiIn.cores[i]] )
     );
-  end
 
-  generate
     if (Cfg.LlcCachePartition) begin : gen_tagger
 
       tagger #(
         .DATA_WIDTH       ( Cfg.AxiDataWidth  ),
         .ADDR_WIDTH       ( Cfg.AddrWidth     ),
-        .MAXPARTITION     ( 8                 ),
-        .AXI_USER_ID_MSB  ( 5                 ),
-        .AXI_USER_ID_LSB  ( 2                 ),
+        .MAXPARTITION     ( Cfg.LlcMaxPartition   ),
+        .AXI_USER_ID_MSB  ( Cfg.LlcUserAmoMsb     ),
+        .AXI_USER_ID_LSB  ( Cfg.LlcUserAmoLsb     ),
         .TAGGER_GRAN      ( 3                 ),
         .axi_req_t        ( axi_mst_req_t     ),
         .axi_rsp_t        ( axi_mst_rsp_t     ),
@@ -809,17 +807,16 @@ module cheshire_soc import cheshire_pkg::*; #(
         .rst_ni,
         .slv_req_i        ( tagger_req                 ),
         .slv_rsp_o        ( tagger_rsp                 ),
-        .mst_req_o        ( axi_in_req[AxiIn.cores]    ),
-        .mst_rsp_i        ( axi_in_rsp[AxiIn.cores]    ),
+        .mst_req_o        ( axi_in_req[AxiIn.cores[i]]    ),
+        .mst_rsp_i        ( axi_in_rsp[AxiIn.cores[i]]    ),
         .cfg_req_i        ( reg_out_req[RegOut.tagger] ),
         .cfg_rsp_o        ( reg_out_rsp[RegOut.tagger] )
       );
     end else begin
-      assign axi_in_req[AxiIn.cores] = tagger_req;
-      assign tagger_rsp = axi_in_rsp[AxiIn.cores];
+      assign axi_in_req[AxiIn.cores[i]] = tagger_req;
+      assign tagger_rsp = axi_in_rsp[AxiIn.cores[i]];
     end
-
-  endgenerate
+  end
 
   /////////////////////////
   //  JTAG Debug Module  //