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Fix include paths in synopsys script #190

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Fix include paths in synopsys script #190

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4 changes: 2 additions & 2 deletions src/script_fmt/synopsys_tcl.tera
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ set search_path_initial $search_path
#}{% for group in srcs %}
set search_path $search_path_initial
{% for incdir in group.incdirs %}{# Add group's include directories
#}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}"
#}lappend search_path "{{ incdir | replace(from=root, to='$ROOT') }}"
{% endfor %}
{% if abort_on_error %}if {0 == [{% endif %}{# Catch errors immediately
#}analyze -format {% if group.file_type == 'verilog' %}sv{% elif group.file_type == 'vhdl' %}vhdl{% endif %} \{# Analyze command for SystemVerilog or VHDL #}
Expand All @@ -24,7 +24,7 @@ set search_path $search_path_initial
#}{% for file in all_verilog %}{# Loop over verilog files
#}{% if loop.first %}set search_path $search_path_initial
{% for incdir in all_incdirs %}{# Add all include directories
#}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}"
#}lappend search_path "{{ incdir | replace(from=root, to='$ROOT') }}"
{% endfor %}
{% if abort_on_error %}if {0 == [{% endif %}{# Catch errors immediately
#}analyze -format sv \{# Analyze command for SystemVerilog #}
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