src/axi_dw_upsizer.sv: avoid unnecessarily wide indices into r_data #362
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Using indices of type `addr_t` (aka `logic [AxiAddrWidth-1:0]`) for indexing into `r_data` causes issues with Verilator v5.028+, as the `r_data` array has only `AxiSlvPortStrbWidth` entries.
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As detailed in #361, Verilator versions v5.028+ have issues with a statement in
axi_dw_upsizer.sv. Contrary to my initial assumption, it seems that the root cause of the problem is actually the width of the data type ofmst_port_offsetandslv_port_offsetand not its sign. Hence, this PR reduces the width of these signals to the width that is actually used and assigned on lines 485 and 486.While this is actually a bug in Verilator, I would be very grateful if the maintainers of this repository are willing to accept this workaround.