[HW] A series of fixes#353

Draft

mp-17 wants to merge 20 commits intomainfrom mperotti/debug

+2,064-1,052

Commits on Jun 27, 2024

Rename CSRs in ara dispatcher

MaistoV
authored and
mp-17
committed
Stall Ara upon operations on vector CSRs

MaistoV
authored and
mp-17
committed
Change "errors" to "exceptions"

MaistoV
authored and
mp-17
committed
Extend and fix Ara exception reporting from VLSU

MaistoV
authored and
mp-17
committed
Set vstart=0 for succesful vector instructions

MaistoV
authored and
mp-17
committed
[hardware] Fix vstart handling in dispatcher
mp-17
committed
[hardware] 🐛 Fix reshuffling bug in dispatcher
mp-17
committed
[hardware] 🐛 Fix eew_q update during reshuffle
mp-17
committed
[hardware] 🐛 Suboptimal fix to reshuffle with LMUL > 1
mp-17
committed
[hardware] 🐛 Fix reshuffle
mp-17
committed
[hardware] 🐛 Consider LMUL when deciding if to reshuffle vd
mp-17
committed
[hardware] Bump CVA6
mp-17
committed
Add time-multiplexing for VCPOP and VFIRST

moimfeld
authored and
mp-17
committed
Mask Unit clean-up

moimfeld
authored and
mp-17
committed
[hardware] 🐛 Fix NP2 slide with unbalanced packets
mp-17
committed
[hardware] Check for LMUL legality only if corresponding vreg is used
mp-17
committed
[hardware] VMSBF does not go through VALU
mp-17
committed
[apps] Add random insn generator for verification
mp-17
committed

Commits on Aug 26, 2024