Skip to content

Commit

Permalink
[CHANGELOG] Update Changelog
Browse files Browse the repository at this point in the history
  • Loading branch information
mp-17 committed Jul 5, 2024
1 parent d0ad020 commit d16eba8
Showing 1 changed file with 5 additions and 0 deletions.
5 changes: 5 additions & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -16,13 +16,17 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
- Set vstart=0 upon succesfull vector instructions
- Fix vstart usage in ara dispatcher
- Fix reshuffle mechanism
- Fix vstart usage for memory operations

### Added

- Plot kernels-Vl performance plot
- Print I$/D$ stall metrics
- Add `spmv`, `conjugate_gradient`, and `gemv` kernels.
- Add multi-precision matmul kernel
- Add MMU interface between Ara and CVA6
- Add virtual->physical address translation for Ara by sharing CVA6 MMU
- Add Ara VLSU support for MMU exceptions

### Changed

Expand All @@ -41,6 +45,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
- Bump CVA6 to version that supports "exceptions" reporting
- VLEN is now a parameter of the ara architecture and does not depend on a define anymore
- vlen_t, as a consequence, is now define within the architecture as a parameter/localparam
- Refactor addrgen module

## 3.0.0 - 2023-09-08

Expand Down

0 comments on commit d16eba8

Please sign in to comment.