Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.

git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.
Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc

If this is your first time using fusesoc, initialize fusesoc. This is needed to be able to pull down fussoc library components referenced by microwatt. Run

fusesoc init
fusesoc fetch uart16550
fusesoc library add microwatt /path/to/microwatt

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100): You may wish to ensure you have installed Digilent Board files or appropriate files for your board first.

fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Linux on Microwatt

Mainline Linux supports Microwatt as of v5.14. The Arty A7 is the best tested platform, but it's also been tested on the OrangeCrab and ButterStick.

Use buildroot to create a userspace

A small change is required to glibc in order to support the VMX/AltiVec-less Microwatt, as float128 support is mandiatory and for this in GCC requires VSX/AltiVec. This change is included in Joel's buildroot fork, along with a defconfig:
```
git clone -b microwatt https://github.com/shenki/buildroot
cd buildroot
make ppc64le_microwatt_defconfig
make
```
The output is output/images/rootfs.cpio.

Build the Linux kernel

git clone https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
cd linux
make ARCH=powerpc microwatt_defconfig
make ARCH=powerpc CROSS_COMPILE=powerpc64le-linux-gnu- \
  CONFIG_INITRAMFS_SOURCE=/buildroot/output/images/rootfs.cpio -j`nproc`

The output is arch/powerpc/boot/dtbImage.microwatt.elf.

Build gateware using FuseSoC

First configure FuseSoC as above.
```
fusesoc run --build --target=arty_a7-100 microwatt --no_bram --memory_size=0
```
The output is build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit.
Program the flash

This operation will overwrite the contents of your flash.

For the Arty A7 A100, set FLASH_ADDRESS to 0x400000 and pass -f a100.

For the Arty A7 A35, set FLASH_ADDRESS to 0x300000 and pass -f a35.
```
microwatt/openocd/flash-arty -f a100 build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit
microwatt/openocd/flash-arty -f a100 dtbImage.microwatt.elf -t bin -a $FLASH_ADDRESS
```
Connect to the second USB TTY device exposed by the FPGA
```
minicom -D /dev/ttyUSB1
```
The gateware has firmware that will look at FLASH_ADDRESS and attempt to parse an ELF there, loading it to the address specified in the ELF header and jumping to it.

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

There are a few instructions still to be implemented:
- Vector/VMX/VSX

Name		Name	Last commit message	Last commit date
Latest commit History 1,321 Commits
.github/workflows		.github/workflows
constraints		constraints
fpga		fpga
hello_world		hello_world
include		include
lib		lib
litedram		litedram
liteeth		liteeth
litesdcard		litesdcard
media		media
micropython		micropython
openocd		openocd
rust_lib_demo		rust_lib_demo
scripts		scripts
sim-unisim		sim-unisim
tests		tests
uart16550		uart16550
verilator		verilator
.gitignore		.gitignore
LICENSE		LICENSE
Makefile		Makefile
README.md		README.md
cache_ram.vhdl		cache_ram.vhdl
common.vhdl		common.vhdl
control.vhdl		control.vhdl
core.vhdl		core.vhdl
core_debug.vhdl		core_debug.vhdl
core_dram_tb.vhdl		core_dram_tb.vhdl
core_flash_tb.vhdl		core_flash_tb.vhdl
core_tb.vhdl		core_tb.vhdl
countbits.vhdl		countbits.vhdl
countbits_tb.vhdl		countbits_tb.vhdl
cr_file.vhdl		cr_file.vhdl
crhelpers.vhdl		crhelpers.vhdl
dcache.vhdl		dcache.vhdl
dcache_tb.vhdl		dcache_tb.vhdl
decode1.vhdl		decode1.vhdl
decode2.vhdl		decode2.vhdl
decode_types.vhdl		decode_types.vhdl
divider.vhdl		divider.vhdl
divider_tb.vhdl		divider_tb.vhdl
dmi_dtm_dummy.vhdl		dmi_dtm_dummy.vhdl
dmi_dtm_ecp5.vhdl		dmi_dtm_ecp5.vhdl
dmi_dtm_tb.vhdl		dmi_dtm_tb.vhdl
dmi_dtm_xilinx.vhdl		dmi_dtm_xilinx.vhdl
dram_tb.vhdl		dram_tb.vhdl
execute1.vhdl		execute1.vhdl
fetch1.vhdl		fetch1.vhdl
foreign_random.vhdl		foreign_random.vhdl
fpu.vhdl		fpu.vhdl
git.vhdl.in		git.vhdl.in
glibc_random.vhdl		glibc_random.vhdl
glibc_random_helpers.vhdl		glibc_random_helpers.vhdl
gpio.vhdl		gpio.vhdl
helpers.vhdl		helpers.vhdl
icache.vhdl		icache.vhdl
icache_tb.vhdl		icache_tb.vhdl
icache_test.bin		icache_test.bin
insn_helpers.vhdl		insn_helpers.vhdl
loadstore1.vhdl		loadstore1.vhdl
logical.vhdl		logical.vhdl
microwatt.core		microwatt.core
mmu.vhdl		mmu.vhdl
multiply-32s.vhdl		multiply-32s.vhdl
multiply.vhdl		multiply.vhdl
multiply_tb.vhdl		multiply_tb.vhdl
nonrandom.vhdl		nonrandom.vhdl
plru_tb.vhdl		plru_tb.vhdl
plrufn.vhdl		plrufn.vhdl
pmu.vhdl		pmu.vhdl
ppc_fx_insns.vhdl		ppc_fx_insns.vhdl
predecode.vhdl		predecode.vhdl
random.vhdl		random.vhdl
register_file.vhdl		register_file.vhdl
rotator.vhdl		rotator.vhdl
rotator_tb.vhdl		rotator_tb.vhdl
run.py		run.py
sim_16550_uart.vhdl		sim_16550_uart.vhdl
sim_bram.vhdl		sim_bram.vhdl
sim_bram_helpers.vhdl		sim_bram_helpers.vhdl
sim_bram_helpers_c.c		sim_bram_helpers_c.c
sim_console.vhdl		sim_console.vhdl
sim_console_c.c		sim_console_c.c
sim_jtag.vhdl		sim_jtag.vhdl
sim_jtag_socket.vhdl		sim_jtag_socket.vhdl
sim_jtag_socket_c.c		sim_jtag_socket_c.c
sim_no_flash.vhdl		sim_no_flash.vhdl
sim_pp_uart.vhdl		sim_pp_uart.vhdl
sim_vhpi_c.c		sim_vhpi_c.c
sim_vhpi_c.h		sim_vhpi_c.h
soc.vhdl		soc.vhdl
spi_flash_ctrl.vhdl		spi_flash_ctrl.vhdl
spi_rxtx.vhdl		spi_rxtx.vhdl
sync_fifo.vhdl		sync_fifo.vhdl
syscon.vhdl		syscon.vhdl
utils.vhdl		utils.vhdl
wishbone_arbiter.vhdl		wishbone_arbiter.vhdl
wishbone_bram_tb.bin		wishbone_bram_tb.bin
wishbone_bram_tb.vhdl		wishbone_bram_tb.vhdl
wishbone_bram_wrapper.vhdl		wishbone_bram_wrapper.vhdl

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