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Fix issue found in random test #2472

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Jun 21, 2024
Merged

Fix issue found in random test #2472

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4bc5cfa
Fix issue found in random test
dd-baoshan Jun 19, 2024
4b53f31
Fix zfinx_reserved_gpr constraint
dd-baoshan Jun 19, 2024
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2 changes: 1 addition & 1 deletion cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv
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Expand Up @@ -430,7 +430,7 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen;
//gprs for floating point instructions
if(RV32ZFINX inside {supported_isa}) begin
foreach(corev_cfg.zfinx_reserved_gpr[i]) begin
if (corev_cfg.zfinx_reserved_gpr[i] inside {ZERO, RA, SP, GP, TP}) continue;
if (corev_cfg.zfinx_reserved_gpr[i] inside {ZERO, corev_cfg.ra, corev_cfg.sp, GP, corev_cfg.tp}) continue;
imm = get_rand_spf_value();
reg_name = corev_cfg.zfinx_reserved_gpr[i].name();
str = $sformatf("%0sli%0s %0s, 0x%0x", indent, indent, reg_name.tolower(), imm);
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2 changes: 1 addition & 1 deletion cv32e40p/env/corev-dv/cv32e40p_instr_gen_config.sv
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Expand Up @@ -158,7 +158,7 @@ class cv32e40p_instr_gen_config extends riscv_instr_gen_config;
zfinx_reserved_gpr.size() == num_zfinx_reserved_reg;
unique {zfinx_reserved_gpr};
foreach(zfinx_reserved_gpr[i]) {
!(zfinx_reserved_gpr[i] inside {ZERO, RA, SP, GP, TP, S0, S1, A0, A1, A2, A3, A4, A5});
!(zfinx_reserved_gpr[i] inside {ZERO, ra, sp, GP, tp, S0, S1, A0, A1, A2, A3, A4, A5});
(zfinx_reserved_gpr[i] != dp);
(zfinx_reserved_gpr[i] != str_rs1);
(zfinx_reserved_gpr[i] != str_rs3);
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15 changes: 7 additions & 8 deletions cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv
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Expand Up @@ -908,6 +908,7 @@ class uvme_rv32x_hwloop_covg # (
if (is_init_mmode_mret && pending_irq_ack) begin
is_init_mmode_mret = 0;
pending_irq_ack = 0;
wait(0); // stop this thread
end
end // INIT_MACHINE_MODE
forever begin : IRQ_PERIOD
Expand Down Expand Up @@ -963,6 +964,8 @@ class uvme_rv32x_hwloop_covg # (
enter_hwloop_sub_cnt++;
if (is_trap && is_dbg_mode && !cv32e40p_rvvi_vif.csr_dcsr_step && enter_hwloop_sub_cnt == 1) begin : TRAP_DUETO_DBG_ENTRY // exception trap and debug are b2b cycles (except debug step)
has_pending_trap_due2_dbg = 1;
enter_hwloop_sub = 0; enter_hwloop_sub_cnt = 0;
is_ebreak = 0; is_ecall = 0; is_illegal = 0; is_trap = 0;
end // TRAP_DUETO_DBG_ENTRY
else if (pc_is_mtvec_addr() && !is_mcause_irq()) begin : EXCEPTION_ENTRY
for (int i=0; i<HWLOOP_NB; i++) begin
Expand All @@ -983,8 +986,8 @@ class uvme_rv32x_hwloop_covg # (
if (prev_is_lpend_main[0] && prev_is_trap) hwloop_stat_main.track_lp_cnt[0]++;
if (prev_is_lpend_main[1] && prev_is_trap) hwloop_stat_main.track_lp_cnt[1]++;
has_pending_trap_due2_irq = 1;
is_ebreak = 0; is_ecall = 0; is_illegal = 0; is_trap = 0;
enter_hwloop_sub = 0; enter_hwloop_sub_cnt = 0;
is_ebreak = 0; is_ecall = 0; is_illegal = 0; is_trap = 0;
pending_irq = 0;
`uvm_info(_header, $sformatf("DEBUG - EXCEPTION Entry is replaced with IRQ Entry (higher priority)"), UVM_DEBUG);
`IF_CURRENT_IS_MAIN_HWLOOP(0, IS_IRQ)
Expand All @@ -1002,13 +1005,9 @@ class uvme_rv32x_hwloop_covg # (
// [optional] todo: mie has effect on irq during exception. Current hwloop tests do not exercise nested irq with mie enabled

check_exception_exit();
if (!(is_ebreak || is_ecall || is_illegal || has_pending_trap_due2_dbg || has_pending_trap_due2_irq)) begin
if (!(is_trap || is_ebreak || is_ecall || is_illegal || has_pending_trap_due2_dbg || has_pending_trap_due2_irq)) begin
enter_hwloop_sub = 0; enter_hwloop_sub_cnt = 0;
end
else if (has_pending_trap_due2_dbg) begin
enter_hwloop_sub = 0; enter_hwloop_sub_cnt = 0;
is_ebreak = 0; is_ecall = 0; is_illegal = 0; is_trap = 0;
end
prev_pc_rdata_sub = cv32e40p_rvvi_vif.pc_rdata;

end // ENTER_HWLOOP_SUB
Expand All @@ -1029,7 +1028,7 @@ class uvme_rv32x_hwloop_covg # (
if (has_pending_trap_due2_irq) begin
assert(prev_pc_rdata_main == cv32e40p_rvvi_vif.pc_rdata);
if (pc_is_mtvec_addr() || (cv32e40p_rvvi_vif.trap && is_trap)) begin is_trap = 1; enter_hwloop_sub = 1; has_pending_trap_due2_irq = 0; continue; end // if pc is exception related
else begin is_ebreak = 0; is_ecall = 0; is_illegal = 0; is_trap = 0; enter_hwloop_sub = 0; has_pending_trap_due2_irq = 0; continue; end // if pc is non-exception related
else begin is_ebreak = 0; is_ecall = 0; is_illegal = 0; is_trap = 0; enter_hwloop_sub = 0; has_pending_trap_due2_irq = 0; end // if pc is non-exception related
end
if (is_dbg_mode) begin
if (prev_is_lpend_main[0] && prev_is_trap && !is_ebreakm) hwloop_stat_main.track_lp_cnt[0]++;
Expand All @@ -1039,7 +1038,7 @@ class uvme_rv32x_hwloop_covg # (
if (has_pending_trap_due2_dbg) begin // e.g exception event intercept with debug step
assert (!dcsr_cause_t'(cv32e40p_rvvi_vif.csr_dcsr_cause) != STEP); // this is not mean for step debug
if (pc_is_mtvec_addr() || (cv32e40p_rvvi_vif.trap && is_trap)) begin is_trap = 1; enter_hwloop_sub = 1; has_pending_trap_due2_dbg = 0; continue; end // if pc is exception related
else begin is_ebreak = 0; is_ecall = 0; is_illegal = 0; is_trap = 0; enter_hwloop_sub = 0; has_pending_trap_due2_dbg = 0; continue; end // if pc is non-exception related
else begin is_ebreak = 0; is_ecall = 0; is_illegal = 0; is_trap = 0; enter_hwloop_sub = 0; has_pending_trap_due2_dbg = 0; end // if pc is non-exception related
end
if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm && cv32e40p_rvvi_vif.insn == TB_INSTR_EBREAK) is_ebreakm = 1; else is_ebreakm = 0;
if (cv32e40p_rvvi_vif.trap) prev_is_trap = 1; else prev_is_trap = 0;
Expand Down