Merge pull request #2193 from silabs-robin/json_vplans_generation

JSON Vplans - Generate From CSV
openhwgroup · Oct 16, 2023 · b8a06d3 · b8a06d3
2 parents 651d10b + 0c89e67
commit b8a06d3
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Showing 9 changed files with 11,924 additions and 2 deletions.
diff --git a/bin/csv2json b/bin/csv2json
@@ -57,11 +57,16 @@ csv_reader   = csv.DictReader(csv_file)
 csv_rows         = []
 csv_row_previous = None
 
+def should_fill_cell(cell_value, previous_row, row_key):
+    cell_is_empty        = not cell_value
+    previous_row_exists  = previous_row
+    column_should_repeat = row_key in ['Feature', 'Verification Goal']
+    return  cell_is_empty  and  previous_row_exists  and  column_should_repeat
+
 for row in csv_reader:
     for key, value in row.items():
-        if not value and csv_row_previous:
+        if should_fill_cell(value, csv_row_previous, key):
             row[key] = csv_row_previous[key]
-            # TODO not for "link-to-cov" etc
 
     csv_rows.append(row)
     csv_row_previous = row

diff --git a/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.json b/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.json
diff --git a/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.json b/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.json
diff --git a/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.json b/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.json
diff --git a/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.json b/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.json
diff --git a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.json b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.json
diff --git a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_PMP.json b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_PMP.json
diff --git a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_UserMode.json b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_UserMode.json
diff --git a/cv32e40s/docs/VerifPlans/Simulation/xsecure/xsecure_vplan.json b/cv32e40s/docs/VerifPlans/Simulation/xsecure/xsecure_vplan.json