Merge pull request #2300 from silabs-mateilga/zcmp_test_update

Zcmp test update

cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.json

@@ -332,7 +332,7 @@
         "Pass/Fail Criteria": "Check against ISS",
         "Test Type": "Directed Non-Self-Checking",
         "Coverage Method": "Testcase",
-        "Link to Coverage": "Coverage hole, evaluate priority",
+        "Link to Coverage": "DTC: pma",
         "": ""
     },
     {
@@ -404,7 +404,7 @@
         "Pass/Fail Criteria": "Check against ISS",
         "Test Type": "Directed Non-Self-Checking",
         "Coverage Method": "Testcase",
-        "Link to Coverage": "Coverage hole, evaluate priority",
+        "Link to Coverage": "DTC: pma",
         "": ""
     },
     {
@@ -464,7 +464,7 @@
         "Pass/Fail Criteria": "Check against ISS",
         "Test Type": "Directed Non-Self-Checking",
         "Coverage Method": "Testcase",
-        "Link to Coverage": "Coverage hole, evaluate priority",
+        "Link to Coverage": "\"push\" and \"pop\" instructions tested, testing every type of instruction is deprioritized",
         "": ""
     },
     {
@@ -524,7 +524,7 @@
         "Pass/Fail Criteria": "Check against ISS",
         "Test Type": "Constrained-Random",
         "Coverage Method": "Functional Coverage",
-        "Link to Coverage": "Coverage hole, evaluate priority",
+        "Link to Coverage": "\"push\" and \"pop\" instructions tested, testing every type of instruction is deprioritized",
         "": ""
     },
     {
@@ -620,7 +620,7 @@
         "Pass/Fail Criteria": "Check against ISS",
         "Test Type": "Directed Non-Self-Checking",
         "Coverage Method": "Testcase",
-        "Link to Coverage": "Coverage hole, evaluate priority",
+        "Link to Coverage": "\"push\" and \"pop\" instructions tested, testing every type of instruction is deprioritized",
         "": ""
     },
     {

cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.csv

@@ -397,9 +397,8 @@ Machine Status Registers",MPRV,,"""dcsr.mprven"" is WARL 1.
 Since ""mprven"" is 1, then ""mstatus.MPRV"" always takes effect in D-mode.","Read ""dcsr.mprven"", check that it is always 1.
 
 40S, be in debug mode, have ""mstatus.MPRV"" disabled, check that all instructions are treated as M-mode. Be in debug mode, have ""mstatus.MPRV"" enabled, have ""mstatus.MPP"" set to M/U-mode (different runs), check that instructions take effect with the modified privilege mode.",Assertion Check,Other,Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_mprven_tied,?,?,?
-Silabs Internal,,Instruction boundaries,Haltreq and stepping,"External debug requests and single stepping can only cause debug entry on ""instruction boundaries"", so a multi-step instruction cannot be interrupted by this.","While single stepping, execute misaligned loads/stores, push/pops, and table jumps, cause an external debug request while the instruction has started its sub operations, check that the external debug request does not interrupt the instructions.",Self Checking Test,Directed Self-Checking,Testcase,TODO: not covered,?,?,?
-Debug 1.0.0,,Instruction boundaries,Synchronous entry,"Trigger matching can cause synchronous debug entry, and can interrupt ""within"" and instruction.","Set up triggers to match the following scenario, execute misaligned loads/stores, push/pops, and table jumps, have a trigger fire while the instruction has started its sub operations, check that the instruction gets interrupted ""midway"" and that debug mode is entered correctly.",Self Checking Test,Directed Self-Checking,Testcase,"DTC: pushpop_debug_triggers
-TODO: Increase coverage by checking triggers at first/last operation",?,?,?
+Silabs Internal,,Instruction boundaries,Haltreq and stepping,"External debug requests and single stepping can only cause debug entry on ""instruction boundaries"", so a multi-step instruction cannot be interrupted by this.","While single stepping, execute misaligned loads/stores, push/pops, and table jumps, cause an external debug request while the instruction has started its sub operations, check that the external debug request does not interrupt the instructions.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2""",?,?,?
+Debug 1.0.0,,Instruction boundaries,Synchronous entry,"Trigger matching can cause synchronous debug entry, and can interrupt ""within"" and instruction.","Set up triggers to match the following scenario, execute misaligned loads/stores, push/pops, and table jumps, have a trigger fire while the instruction has started its sub operations, check that the instruction gets interrupted ""midway"" and that debug mode is entered correctly.",Self Checking Test,Directed Self-Checking,Testcase,DTC: pushpop_debug_triggers,?,?,?
 "RISC-V External Debug Support Version 0.13.2
 CV32E40P doc rev 46711ac","4.8.1 DCSR
 

cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.json

@@ -1644,7 +1644,7 @@
         "Pass/Fail Criteria": "Self Checking Test",
         "Test Type": "Directed Self-Checking",
         "Coverage Method": "Testcase",
-        "Link to Coverage": "TODO: not covered",
+        "Link to Coverage": "Covered in DTC \"debug_test2\"",
         "Review (Marton)": "?",
         "Review (Robin)": "?",
         "Review (Henrik)": "?"
@@ -1659,7 +1659,7 @@
         "Pass/Fail Criteria": "Self Checking Test",
         "Test Type": "Directed Self-Checking",
         "Coverage Method": "Testcase",
-        "Link to Coverage": "DTC: pushpop_debug_triggers\nTODO: Increase coverage by checking triggers at first/last operation",
+        "Link to Coverage": "DTC: pushpop_debug_triggers",
         "Review (Marton)": "?",
         "Review (Robin)": "?",
         "Review (Henrik)": "?"

cv32e40s/tests/programs/custom/debug_test2/debug_test2.c

@@ -33,7 +33,7 @@
 
 // MUST be 31 or less (bit position-1 in result array determines test pass/fail
 // status, thus we are limited to 31 tests with this construct.
-#define NUM_TESTS 19
+#define NUM_TESTS 21
 // Start at 1 (ignore dummy test that is only used for env sanity checking during dev.)
 #define START_TEST_NUM 1
 // Abort test at first self-check fail, useful for debugging.
@@ -379,6 +379,8 @@ volatile uint32_t * volatile g_trigger_matched;
 volatile uint32_t * volatile g_has_clic;
 volatile uint32_t * volatile g_single_step_unspec_err;
 
+volatile uint32_t            g_pushpop_area [64];
+
 extern volatile uint32_t *trigger_loc;
 extern volatile uint32_t *trigger_loc_dbg;
 extern volatile uint32_t *trigger_exit;
@@ -465,6 +467,8 @@ uint32_t check_stopcnt_bits(uint32_t index, uint8_t report_name);
 uint32_t single_step(uint32_t index, uint8_t report_name);
 uint32_t mprv_dret_to_umode(uint32_t index, uint8_t report_name);
 uint32_t cover_known_iss_mismatches(uint32_t index, uint8_t report_name);
+uint32_t push_haltreq(uint32_t index, uint8_t report_name);
+uint32_t pop_haltreq(uint32_t index, uint8_t report_name);
 
 // ---------------------------------------------------------------
 // Prototypes for functions that are test specific and
@@ -621,7 +625,7 @@ int main(int argc, char **argv){
   setup_clic();
 
   // Add function pointers to new tests here
-  tests[0]  = dummy; // unused, can be used for env sanity checking
+  tests[0] = dummy; // unused, can be used for env sanity checking
   tests[1]  = debug_csr_rw;
   tests[2]  = trigger_default_val;
   tests[3]  = ebreak_behavior_m_mode;
@@ -640,6 +644,8 @@ int main(int argc, char **argv){
   tests[16] = single_step;
   tests[17] = mprv_dret_to_umode;
   tests[18] = cover_known_iss_mismatches;
+  tests[19] = push_haltreq;
+  tests[20] = pop_haltreq;
 
   // Run all tests in list above
   cvprintf(V_LOW, "\nDebug test start\n\n");
@@ -1134,6 +1140,115 @@ uint32_t request_ebreak_3x(uint32_t index, uint8_t report_name) {
 
 // -----------------------------------------------------------------------------
 
+uint32_t push_haltreq(uint32_t index, uint8_t report_name) {
+  volatile uint8_t test_fail = 0;
+  volatile debug_req_control_t debug_req_ctrl;
+
+  SET_FUNC_INFO
+
+  if (report_name) {
+    cvprintf(V_LOW, "\"%s\"", name);
+    return 0;
+  }
+
+  debug_req_ctrl = (debug_req_control_t) {
+    .fields.value            = 1,
+    .fields.pulse_mode       = 1,
+    .fields.rand_pulse_width = 0,
+    .fields.pulse_width      = 0x1fff,
+    .fields.rand_start_delay = 0,
+    .fields.start_delay      = 15
+  };
+
+  *g_debug_test_num = 19;
+  *g_debug_status = 0;
+  DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw;
+
+  __asm__ volatile(
+    R"(
+      # Save old "sp"
+      mv t0, sp
+
+      # Setup temporary "sp"
+      la sp, g_pushpop_area
+      addi sp, sp, 64
+
+      # Push to temporary "sp"
+      cm.push {x1, x8-x9, x18-x27}, -64
+
+      # Restore old "sp"
+      mv sp, t0
+    )"::: "t0"
+  );
+
+  test_fail += *g_debug_status == 1 ? 0 : 1;
+  *g_debug_status = 0;
+
+  if (test_fail) {
+    cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name);
+    return index + 1;
+  }
+  cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name);
+  return 0;
+}
+
+
+// -----------------------------------------------------------------------------
+
+uint32_t pop_haltreq(uint32_t index, uint8_t report_name) {
+  volatile uint8_t test_fail = 0;
+  volatile debug_req_control_t debug_req_ctrl;
+
+  SET_FUNC_INFO
+
+  if (report_name) {
+    cvprintf(V_LOW, "\"%s\"", name);
+    return 0;
+  }
+
+  debug_req_ctrl = (debug_req_control_t) {
+    .fields.value            = 1,
+    .fields.pulse_mode       = 1,
+    .fields.rand_pulse_width = 0,
+    .fields.pulse_width      = 0x1fff,
+    .fields.rand_start_delay = 0,
+    .fields.start_delay      = 25
+  };
+
+  *g_debug_test_num = 20;
+  *g_debug_status = 0;
+  DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw;
+
+  __asm__ volatile(
+    R"(
+        # Save old "sp" and GPRs
+      cm.push {x1, x8-x9}, -16
+      mv t0, sp
+
+      # Setup temporary "sp"
+      la sp, g_pushpop_area
+
+      # Pop from temporary "sp"
+      cm.pop {x1, x8-x9, x18-x27}, 64
+
+      # Restore old "sp" and GPRs
+      mv sp, t0
+      cm.pop {x1, x8-x9}, 16
+    )"::: "t0"
+  );
+
+  test_fail += *g_debug_status == 1 ? 0 : 1;
+  *g_debug_status = 0;
+
+  if (test_fail) {
+    cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name);
+    return index + 1;
+  }
+  cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name);
+  return 0;
+}
+// -----------------------------------------------------------------------------
+
 __attribute__((naked)) void m_fast14_irq_handler(void) {
 
   __asm__ volatile ( R"(
@@ -1455,6 +1570,10 @@ void __attribute__((naked)) _debugger_start(void) {
     beq s0, s1, 14f
     addi s0, zero, 18
     beq s0, s1, 18f
+    addi s0, zero, 19
+    beq s0, s1, 19f
+    addi s0, zero, 20
+    beq s0, s1, 20f
 
     # no match, exit
     beq zero, zero, 99f
@@ -1498,6 +1617,12 @@ void __attribute__((naked)) _debugger_start(void) {
     18: call cover_known_iss_mismatches_dbg
     beq zero, zero, 99f
 
+    19: call request_hw_debugger_dbg
+    beq zero, zero, 99f
+
+    20: call request_hw_debugger_dbg
+    beq zero, zero, 99f
+
     99: call _debugger_end
     dret