Merge pull request #2506 from XavierAubert/cv32e40p/closure

Preparation for cv32e40pv1.8.3 tag

CONTRIBUTING.md

@@ -18,11 +18,11 @@ All pull-requests to OpenHW Group git repositories must be signed-off using the
 `--signoff` (or `-s`) option to the git commit command (see below).
 
 ## Branches
-The core-v-verif repository provides testbenches for multiple OpenHW cores.  As such the core-v-verif repository uses branches for maintaining stability between 
-the different core testbenches as well as recognizing independent development streams.  An adapted form of the Git Flow is used in this repository.  
+The core-v-verif repository provides testbenches for multiple OpenHW cores.  As such the core-v-verif repository uses branches for maintaining stability between
+the different core testbenches as well as recognizing independent development streams.  An adapted form of the Git Flow is used in this repository.
 
 The following are the official branches for core-v-verif
- Branch                | Example (if applicable) | Usage               
+ Branch                | Example (if applicable) | Usage
  --------------------- | ----------------------- | -----------------------
 _\<core>_/dev          | cv32e40p/dev            | Main line of development for a core testbench.  Most contributinos should target a dev branch.
 _\<core>_/release      | cv32e40p/release        | Staging branch for merge dev branches into master (and vice versa).  In general only OpenHW Committers will utilize these branches
@@ -32,15 +32,15 @@ In most cases a contribution should be made on a _dev_ branch.<br>
 Common infrastructure fixes and updates may target the _master_ branch using the hotfix flow to directly address issues requiring timely fixes.<br>
 
 More information on core-v-verif branch usage can be found here:
-https://github.com/openhwgroup/core-v-docs/blob/master/verif/Common/Presentations/20210311-Branches%20and%20CIs%20for%20core-v-verif.pptx
+https://github.com/openhwgroup/core-v-docs/blob/cv32e40p_v1.8.3/TGs/verification-task-group/documents/presentations/20210311-Branches_and_CIs_for_core-v-verif.pptx
 
 ## The Mechanics
 1. [Fork](https://help.github.com/articles/fork-a-repo/) the [core-v-verif](https://github.com/openhwgroup/core-v-verif) repository
 2. Clone repository: `git clone https://github.com/[your_github_username]/core-v-verif`
 3. Checkout the correct branch reflecting the nature of your contribution.  Nearly all contributions should target a core's _dev_ branch.  Hotfixes can target _master_.
-4. Create your feature branch: `git checkout -b <my_branch>.`<br> Please uniquify your branch name.  See the [Git Cheats](https://github.com/openhwgroup/core-v-verif/blob/master/GitCheats.md) for a useful nominclature.
-5. Test your changes with the [ci_check](https://github.com/openhwgroup/core-v-verif/blob/master/bin/ci_check) script.
+4. Create your feature branch: `git checkout -b <my_branch>.`<br> Please uniquify your branch name.  See the [Git Cheats](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/GitCheats.md) for a useful nominclature.
+5. Test your changes with the [ci_check](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/bin/ci_check) script.
 6. Commit your changes: `git commit -m 'Add some feature' --signoff`<br>...take note of that **--signoff**, it's important!
 7. Push feature branch: `git push origin <my_branch>`
 8. Submit a [pull request](https://help.github.com/en/github/collaborating-with-issues-and-pull-requests/creating-a-pull-request-from-a-fork).
-9. If known, it is advisable to select one or more appropriate reviewers for your PR.  For hotfix PRs, request either Steve Richmond or Mike Thompson for proper review.
+9. If known, it is advisable to select one or more appropriate reviewers for your PR.  For hotfix PRs, request either Steve Richmond or Mike Thompson for proper review.

GitCheats.md

@@ -1,6 +1,6 @@
 # Git cheat-sheet.
 A few examples to illustrate use of `git` on the command-line.<br><br>
-PLEASE READ CAREFULLY the [CONTRIBUTING.md](https://github.com/openhwgroup/core-v-verif/blob/master/CONTRIBUTING.md)
+PLEASE READ CAREFULLY the [CONTRIBUTING.md](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/CONTRIBUTING.md)
 file in this directory.  You must follow the specified flow to contribute to this repository.
 
 If you have a suggestion to improve this document please either submit a pull-request, open an issue or email [email protected].
@@ -145,4 +145,3 @@ $ git remote -v<br>
   \> metrics [email protected]:cv32e40p_verif/cv32e40p_verif.git (push)<br>
   \> origin  https://github.com/openhwgroup/core-v-verif (fetch)<br>
   \> origin  https://github.com/openhwgroup/core-v-verif (push)<br>
-

MergeTest.md

@@ -1,7 +1,7 @@
 # Merge Test
 Use this file to exercise the GitHub portions of the OpenHW Group workflow.
 
-Parts of the [OpenHW Group workflow](https://github.com/openhwgroup/core-v-docs/blob/master/verif/Common/OpenHWGroup_WorkFlow.pdf)
+Parts of the [OpenHW Group workflow](https://github.com/openhwgroup/programs/blob/cv32e40p_v1.8.3/TGs/verification-task-group/documents/presentations/OpenHWGroup_WorkFlow.pdf)
 are modeled after Vincent Driessen's [git branching model](https://nvie.com/posts/a-successful-git-branching-model/).  When
 you first register as a member of OpenHW, you can use this file to safely test whether you have the appropriate GitHub contributor priviledges for this repo.   Try this:
 * Fork the repository: https://help.github.com/en/github/getting-started-with-github/fork-a-repo
@@ -13,12 +13,11 @@ you first register as a member of OpenHW, you can use this file to safely test w
 
 When all of that works, you are ready to make contributions to the OpenHW Group CORE-V projects.
 
-If you are new to git, or unfamiliar with using branches and pull-requests, have a look at our [Git Cheat Sheet](https://github.com/openhwgroup/core-v-verif/blob/master/GitCheats.txt).
+If you are new to git, or unfamiliar with using branches and pull-requests, have a look at our [Git Cheat Sheet](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/GitCheats.md).
 
 ## Make your changes below this line.
 Extra marks for creativity and wit.
 
-
 ### Madcat
 ```
             /^v^\
@@ -46,39 +45,39 @@ Extra marks for creativity and wit.
       >_<          >_<
      || ||        || ||
      || ||        || ||
-     || ||        || ||    -- Jay Thaler 
+     || ||        || ||    -- Jay Thaler
    __|\_/|__    __|\_/|__     -- David Poulin
   /___n_n___\  /___n_n___\
   ```
 
 ### Gecko
 ```
-                                                         ## ##                  
-                                                       ##### *                  
-                                                        ###/                    
-                                                     #####                      
-                             *#########        ########.                        
-                           ########################                             
-                       ###############################                          
-                     #####&@&&&&&&&&%################(((/                       
-                                      %%%##########((((((((                     
-            (                            %######((((((((((((                    
-           (                              ###((((((((((((((((.                  
-          (                               ((((   (((((((((((((                  
-         (                         *#   ((((      (((((((((((((                 
-        ((                       ###((((           (((((((((((((                
-        ((                      *  ((               ((((((((((((                
-        /(                                    (((((  (((((((((((                
-        /((                                (( (((((((((((((((((((((((((         
-         /((                            ,((((((((((((((((//((((((((((((         
-          //(                               (.(    ((((((////////((((((  ((     
-          ,////                         (((   ((    (((((//////     /////////   
-            /////                                   ((((/////       /   /*      
-             ///////                             (((((/////        //    //     
-               ////////.                     /((((((/////                       
-                  **///////////,     *((((((((((//////                          
-                     ****//////////((((((((////////                             
-                          /*******************                               
+                                                         ## ##
+                                                       ##### *
+                                                        ###/
+                                                     #####
+                             *#########        ########.
+                           ########################
+                       ###############################
+                     #####&@&&&&&&&&%################(((/
+                                      %%%##########((((((((
+            (                            %######((((((((((((
+           (                              ###((((((((((((((((.
+          (                               ((((   (((((((((((((
+         (                         *#   ((((      (((((((((((((
+        ((                       ###((((           (((((((((((((
+        ((                      *  ((               ((((((((((((
+        /(                                    (((((  (((((((((((
+        /((                                (( (((((((((((((((((((((((((
+         /((                            ,((((((((((((((((//((((((((((((
+          //(                               (.(    ((((((////////((((((  ((
+          ,////                         (((   ((    (((((//////     /////////
+            /////                                   ((((/////       /   /*
+             ///////                             (((((/////        //    //
+               ////////.                     /((((((/////
+                  **///////////,     *((((((((((//////
+                     ****//////////((((((((////////
+                          /*******************
 
 ```
 {signal: [

NEWS_ARCHIVE.md

@@ -1,15 +1,14 @@
 ### NEWS UPDATES (going back to early 2020):
 **2020-12-10**: OpenHW formally decalres [RTL Freeze for CV32E40P](https://www.openhwgroup.org/news/2020/12/10/core-v-cve4-rtl-freeze-milestone-achieved/)
 <br>
-**2020-10-15**: Aldec's Riviera-PRO SystemVerilog simulator is now supported by core-v-verif.  Check out the README in [mk/uvmt](https://github.com/openhwgroup/core-v-verif/tree/master/mk/uvmt#running-the-environment-with-aldec-riviera-pro-riviera) for more information.
+**2020-10-15**: Aldec's Riviera-PRO SystemVerilog simulator is now supported by core-v-verif.  Check out the README in [mk](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/mk/#running-the-environment-with-aldec-riviera-pro-riviera) for more information.
 <br>
-**2020-09-04**: a new (and _much_ better) method of specifying and organizating test-programs and simulations is now merged in.  See slide "_Test Specification Updates_" in the [2020-08-31 CV32E40P project update](https://github.com/openhwgroup/core-v-docs/blob/master/verif/MeetingPresentations/20200831-CV32E40P-ProjectScheduleUpdate.pptx).
+**2020-09-04**: a new (and _much_ better) method of specifying and organizating test-programs and simulations is now merged in.  See slide "_Test Specification Updates_" in the [2020-08-31 CV32E40P project update](https://github.com/openhwgroup/programs/blob/cv32e40p_v1.8.3/TGs/verification-task-group/projects/CV32E40P_v1.0.0/documents/20200831-CV32E40P-ProjectScheduleUpdate.pptx).
 <br>
-**2020-06-12**: a new "Board Support Package" for CV32E40P simulations is installed at `cv32/bsp`.  This BSP should be used to compile/assemble your [test-programs](https://core-v-docs-verif-strat.readthedocs.io/en/latest/test_program_environment.html).  The Makefiles for both the CORE testbench and UVM verification environment have been updated to use this BSP.
+**2020-06-12**: a new "Board Support Package" for CV32E40P simulations is installed at `cv32/bsp`.  This BSP should be used to compile/assemble your [test-programs](https://docs.openhwgroup.org/projects/core-v-verif/en/latest/test_programs.html).  The Makefiles for both the CORE testbench and UVM verification environment have been updated to use this BSP.
 <br>
 **2020-06-02:** The [Imperas OVPsim Instruction Set Generator](http://www.ovpworld.org/) has been integrated into the UVM environment as the Referenece Model for the CV32E40(P).  You will need to obtain a license from Imperas to use it.
 <br>
-**2020-02-28:** The OpenHW Group CV32E40P is now live!<br>This repository no longer contains a local copy of the RTL.  The RTL is cloned from the appropriate [core-v-cores](https://github.com/openhwgroup/core-v-cores) repository as needed.  The specific branch and hash of the RTL is controlled by a set of variables in `cv32e40p/sim/Common.mk`.
+**2020-02-28:** The OpenHW Group CV32E40P is now live!<br>This reposito of variables in `cv32e40p/sim/Common.mk`.ry no longer contains a local copy of the RTL.  The RTL is cloned from the appropriate [core-v-cores](https://github.com/openhwgroup/core-v-cores) repository as needed.  The specific branch and hash of the RTL is controlled by a set
 <br>
 **2020-02-10:** The core-v-verif repository now supports multiple cores.  The previously named cv32 directory is now cv32e40p to represent the testbench for the CV32E40P core.  Future cores will be verified in respectively named directories in core-v-verif as siblings to cva6 and cv32e40p.
-

README.md

@@ -23,14 +23,15 @@ Functional verification project for the CORE-V family of RISC-V cores.
 
 <!--
 ## NEWS UPDATES:
+**2024-07-01**: CV32E40Pv2 has reached RTL freeze [CV32E40Pv2 final RTL Freeze status](https://github.com/openhwgroup/programs/blob/cv32e40p_v1.8.3/TGs/cores-task-group/MeetingPresentations/Cores-TG-07.01.2024.pdf)
 **2021-07-15**: The verificaton environment for the [cv32e40s](https://github.com/openhwgroup/cv32e40s) is up and running.
 <br>
 **2021-03-23**: The verificaton environment for the [cv32e40x](https://github.com/openhwgroup/cv32e40x) is up and running.
 <br>
 **2020-12-16**: The [cv32e40p_v1.0.0](https://github.com/openhwgroup/core-v-verif/releases/tag/22dc5fc) of core-v-verif is released.
 This tag clones the v1.0.0 release of the CV32E40P CORE-V core and will allow you to reproduce the verification environment as it existed at `RTL Freeze`.
 <br>
-More news is available in the [archive](https://github.com/openhwgroup/core-v-verif/blob/master/NEWS_ARCHIVE.md).
+More news is available in the [archive](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/NEWS_ARCHIVE.md).
 -->
 
 ## Getting Started
@@ -83,8 +84,8 @@ We highly appreciate community contributions. You can get a sense of our current
 within a project are defined as [issues](https://github.com/openhwgroup/core-v-verif/issues) with a `task` label.
 <br><br>To ease our work of reviewing your contributions, please:
 
-* Review [CONTRIBUTING](https://github.com/openhwgroup/core-v-verif/blob/master/CONTRIBUTING.md)
-and our [SV/UVM coding style guidelines](https://github.com/openhwgroup/core-v-verif/blob/master/docs/CodingStyleGuidelines.md).
+* Review [CONTRIBUTING](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/CONTRIBUTING.md)
+and our [SV/UVM coding style guidelines](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/docs/CodingStyleGuidelines.md).
 * Split large contributions into smaller commits addressing individual changes or bug fixes.
 Do not mix unrelated changes into the same commit!
 * Write meaningful commit messages.