Merge pull request #2281 from silabs-hfegran/dev_hf_cov_fixup

Coverage & decoder fixup
openhwgroup · Nov 7, 2023 · 233cb1f · 233cb1f
2 parents dc6620e + 9aee3e5
commit 233cb1f
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Showing 3 changed files with 25 additions and 6 deletions.
diff --git a/cv32e40s/env/uvme/cov/uvme_exceptions_covg.sv b/cv32e40s/env/uvme/cov/uvme_exceptions_covg.sv
@@ -21,11 +21,11 @@ covergroup cg_exceptions
 
   `per_instance_fcov
 
-  cp_trap : coverpoint isacov.instr.rvfi.trap {
+  cp_trap : coverpoint isacov.instr.rvfi.trap.trap {
     bins trap = {1};
   }
-  cp_intr : coverpoint isacov.instr.rvfi.intr {
-    bins intr = {1};
+  cp_intr : coverpoint isacov.instr.rvfi.intr.interrupt {
+    bins interrupt = {1};
   }
   cp_imm12 : coverpoint isacov.instr.csr_val {
     bins imm12[16] = {[0:$]};
@@ -41,15 +41,17 @@ covergroup cg_exceptions
   cp_no_ebreakm : coverpoint (isacov.instr.rvfi.csrs["dcsr"].get_csr_retirement_data()[15]) {
     bins no_ebreakm = {0};
   }
-  cp_mcause : coverpoint isacov.instr.rvfi.csrs["mcause"].get_csr_retirement_data() {
+  cp_mcause : coverpoint isacov.instr.rvfi.csrs["mcause"].get_csr_retirement_data()[10:0] {
     bins reset               = {0};
     bins ins_acc_fault       = {1};
     bins illegal_ins         = {2};
     bins breakpoint          = {3};
     bins load_acc_fault      = {5};
     bins store_amo_acc_fault = {7};
+    bins ecall_umode         = {8};
     bins ecall               = {11};
-    bins ins_bus_fault       = {48};
+    bins ins_bus_fault       = {24};
+    bins ins_parity_fault    = {25};
   }
   cp_pcr_mtvec : coverpoint (isacov.instr.rvfi.pc_rdata[31:2] == isacov.instr.rvfi.csrs["mtvec"].get_csr_retirement_data()[31:2]) {
     bins one = {1};

diff --git a/lib/isa_decoder/isa_decoder.sv b/lib/isa_decoder/isa_decoder.sv
@@ -635,6 +635,22 @@
           asm.rs1.valid           = 1;
           asm.rs1.valid_gpr_rvc   = 1;
           asm.imm.valid           = 1;
+        end else if (name inside { C_ANDI }) begin
+          asm.rd.gpr              = get_gpr_from_gpr_rvc(instr.compressed.format.cb.rd_rs1.gpr);
+          asm.rd.gpr_rvc          = instr.compressed.format.cb.rd_rs1.gpr;
+          asm.rs1.gpr             = get_gpr_from_gpr_rvc(instr.compressed.format.cb.rd_rs1.gpr);
+          asm.rs1.gpr_rvc         = instr.compressed.format.cb.rd_rs1.gpr;
+          asm.imm.imm_raw         = { instr.compressed.format.cb.offset_12_10[12], instr.compressed.format.cb.offset_6_2 };
+          asm.imm.imm_raw_sorted  = { instr.compressed.format.cb.offset_12_10[12], instr.compressed.format.cb.offset_6_2 };
+          asm.imm.imm_type        = IMM;
+          asm.imm.width           = 6;
+          asm.imm.sign_ext        = 1;
+          asm.imm.imm_value       = get_imm_value_cb({ instr.compressed.format.cb.offset_12_10[12], instr.compressed.format.cb.offset_6_2 });
+          asm.rd.valid            = 1;
+          asm.rd.valid_gpr_rvc    = 1;
+          asm.rs1.valid           = 1;
+          asm.rs1.valid_gpr_rvc   = 1;
+          asm.imm.valid           = 1;
         end
       end
       CJ_TYPE: begin

diff --git a/lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv b/lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv
@@ -216,7 +216,8 @@ function void uvma_isacov_mon_c::write_rvfi_instr(uvma_rvfi_instr_seq_item_c#(IL
     // might also interfere with the spike implementation.
     // the "get_rx"-functions should no longer be needed if we supply the translated values to
     // the coverage model.
-    mon_trn.instr.c_rdrs1 = instr_asm.rd.valid_gpr_rvc  ? instr_asm.rd.gpr_rvc  : instr_asm.rd.gpr;
+    mon_trn.instr.c_rdrs1 = instr_asm.rd.valid ? ( instr_asm.rd.valid_gpr_rvc  ? instr_asm.rd.gpr_rvc  : instr_asm.rd.gpr )
+                                               : ( instr_asm.rs1.valid_gpr_rvc ? instr_asm.rs1.gpr_rvc : instr_asm.rs1.gpr );
     mon_trn.instr.c_rdp   = instr_asm.rd.valid_gpr_rvc  ? instr_asm.rd.gpr_rvc  : instr_asm.rd.gpr;
     mon_trn.instr.c_rs1s  = instr_asm.rs1.valid_gpr_rvc ? instr_asm.rs1.gpr_rvc : instr_asm.rs1.gpr;
     mon_trn.instr.c_rs2s  = instr_asm.rs2.valid_gpr_rvc ? instr_asm.rs2.gpr_rvc : instr_asm.rs2.gpr;