benchdnn: reorder: add f4_e3m0 coverage

oneapi-src · Dec 20, 2024 · 339842f · 339842f
1 parent 1f704c4
commit 339842f
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Showing 3 changed files with 8 additions and 4 deletions.
diff --git a/tests/benchdnn/dnnl_common.cpp b/tests/benchdnn/dnnl_common.cpp
@@ -665,7 +665,7 @@ void skip_unimplemented_data_type(
     const bool has_f4_e2m1_support
             = is_gpu() || (is_cpu() && has_data_type_support(dnnl_f4_e2m1));
     const bool has_f4_e3m0_support
-            = is_gpu() || (is_cpu() && has_data_type_support(dnnl_f4_e3m0));
+            = (is_cpu() && has_data_type_support(dnnl_f4_e3m0));
     const bool has_f8_e5m2_support = is_gpu()
             || (is_cpu() && has_data_type_support(dnnl_f8_e5m2)
                     && (dir & FLAG_INF));
@@ -677,7 +677,7 @@ void skip_unimplemented_data_type(
     // f16 is supported on GPU for inference only.
     const bool has_f16_support = is_gpu() && (dir & FLAG_FWD);
     const bool has_f4_e2m1_support = is_gpu();
-    const bool has_f4_e3m0_support = is_gpu();
+    const bool has_f4_e3m0_support = false;
     const bool has_e8m0_support = is_gpu();
     const bool has_f8_e5m2_support = is_gpu();
     const bool has_f8_e4m3_support = is_gpu();

diff --git a/tests/benchdnn/inputs/reorder/test_reorder_fp4 b/tests/benchdnn/inputs/reorder/test_reorder_fp4
@@ -1,6 +1,6 @@
 --reset
 --sdt=f32
---ddt=f4_e2m1
+--ddt=f4_e2m1,f4_e3m0
 --stag=bax,abx
 --dtag=abx,bax 2x64x14x14 2x56x14x14
 --dtag=abx,bax 2x64x64x3x3 2x56x56x3x3
@@ -9,7 +9,7 @@
 --dtag=gOIhw16i16o,gOIhw2i4o2i,gOIhw2o4i2o,gOIhw4o8i2o 4x16x16x3x3
 
 --reset
---sdt=f4_e2m1
+--sdt=f4_e2m1,f4_e3m0
 --ddt=f32
 --dtag=abx,bax
 --stag=bax,abx 2x64x14x14 2x56x14x14

diff --git a/tests/benchdnn/reorder/cfg.cpp b/tests/benchdnn/reorder/cfg.cpp
@@ -28,6 +28,7 @@ namespace reorder {
 
 const float int_max_exact = 1 << 24;
 const float f16_max_exact = 1 << 11;
+const float f4_max_exact = 1 << 3;
 
 #define REG(dt, min, max) \
     const dt_conf_s CONCAT2(_conf_, dt) = {CONCAT2(dnnl_, dt), min, max}; \
@@ -40,6 +41,7 @@ REG(bf16, -int_max_exact, int_max_exact);
 REG(f8_e5m2, -f16_max_exact, f16_max_exact);
 REG(f8_e4m3, -f16_max_exact, f16_max_exact);
 REG(f4_e2m1, -f16_max_exact, f16_max_exact);
+REG(f4_e3m0, -f4_max_exact, f4_max_exact);
 // Do not exceed max float value representable in integer. Otherwise, we get
 // a correctness issue caused by different computations in reference and the
 // library.
@@ -61,6 +63,7 @@ dt_conf_t dt2cfg(dnnl_data_type_t dt) {
     CASE(f8_e5m2);
     CASE(f8_e4m3);
     CASE(f4_e2m1);
+    CASE(f4_e3m0);
     CASE(s32);
     CASE(s8);
     CASE(u8);
@@ -81,6 +84,7 @@ dnnl_data_type_t cfg2dt(dt_conf_t cfg) {
     CASE(f8_e5m2);
     CASE(f8_e4m3);
     CASE(f4_e2m1);
+    CASE(f4_e3m0);
     CASE(s32);
     CASE(s8);
     CASE(u8);