src: gpu: add reliable xe_lpg arch detection

src/gpu/compute/device_info.hpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
-* Copyright 2019-2023 Intel Corporation
+* Copyright 2019-2024 Intel Corporation
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
@@ -255,6 +255,8 @@ struct device_info_t {
 
     bool mayiuse_systolic() const { return mayiuse_systolic_; }
 
+    bool is_xelpg() const { return is_xelpg_; }
+
     bool mayiuse_non_uniform_work_groups() const {
         return mayiuse_non_uniform_work_groups_;
     }
@@ -290,6 +292,7 @@ struct device_info_t {
     int stepping_id_ = 0;
     bool mayiuse_systolic_ = false;
     bool mayiuse_ngen_kernels_ = false;
+    bool is_xelpg_ = false;
 
     std::string name_;
     runtime_version_t runtime_version_;

src/gpu/jit/codegen/codegen.cpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
-* Copyright 2023 Intel Corporation
+* Copyright 2023-2024 Intel Corporation
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
@@ -52,7 +52,8 @@ class ir_to_ngen_t : public ir_visitor_t {
         : host_(host)
         , expr_binding_(expr_binding)
         , simd_size_(host->getSIMD())
-        , eu_count_(host->exec_cfg_.hw().eu_count()) {}
+        , eu_count_(host->exec_cfg_.hw().eu_count())
+        , is_xelpg_(host->exec_cfg_.hw().is_xelpg()) {}
 
     ~ir_to_ngen_t() {
 #ifdef DNNL_DEV_MODE
@@ -674,7 +675,8 @@ class ir_to_ngen_t : public ir_visitor_t {
         }
         if ((hw <= ngen::HW::XeLP && send_func.is_atomic())
                 || (hw == ngen::HW::XeHPG && send_func.is_atomic()
-                        && send_func.type.kind() == type_kind_t::qword)) {
+                        && send_func.type.kind() == type_kind_t::qword
+                        && !is_xelpg_)) {
             send_atomic_add_emu(scope, send_func, mask_op, mod, mem_buf_rd,
                     surf_bti, mem_off_op.reg_data(), rd);
         } else {
@@ -764,6 +766,7 @@ class ir_to_ngen_t : public ir_visitor_t {
     expr_binding_t expr_binding_;
     int simd_size_;
     int eu_count_;
+    bool is_xelpg_;
 
 #ifdef DNNL_DEV_MODE
     int bank_conflicts_ = 0;

src/gpu/jit/conv/config.cpp

@@ -836,10 +836,9 @@ bool data_types_ok(const conv_problem_t &prb, const hw_t &hw) {
     bool is_hf8 = utils::one_of(data_type::f8_e4m3, src, wei, dst, bia);
     if (!prb.is_f64_conv() && utils::one_of(data_type::f64, src, wei, dst, bia))
         return false;
-    bool is_xelpg = hw == ngen::HW::XeHPG && !hw.systolic_support();
     if (prb.is_f64_conv()
             && (utils::one_of(hw.to_ngen(), ngen::HW::XeLP, ngen::HW::XeHPG)
-                    && !is_xelpg))
+                    && !hw.is_xelpg()))
         return false;
     if (is_bf8
             && !(utils::one_of(hw, ngen::HW::XeHPC) && hw.systolic_support()))

src/gpu/jit/ir/hw.hpp

@@ -85,6 +85,7 @@ class hw_t {
                 device_info->max_wg_size(/*large_grf_mode=*/false));
         large_grf_support_ = compute_engine->mayiuse_large_grf_mode();
         systolic_support_ = device_info->mayiuse_systolic();
+        is_xelpg_ = device_info->is_xelpg();
 
 #ifdef DNNL_DEV_MODE
         gpu_arch_t old_arch = gpu_arch;
@@ -98,6 +99,7 @@ class hw_t {
     }
 
     bool is_undef() const { return hw_ == ngen::HW::Unknown; }
+    bool is_xelpg() const { return is_xelpg_; }
     ngen::HW to_ngen() const { return hw_; }
     int stepping_id() const { return stepping_id_; }
     int eu_count() const { return eu_count_; }
@@ -196,6 +198,7 @@ class hw_t {
     int max_wg_size_ = 0;
     bool large_grf_support_ = false;
     bool systolic_support_ = false;
+    bool is_xelpg_ = false;
 };
 
 inline hw_t str_to_hw(const std::string &s) {

src/gpu/ocl/ocl_gpu_device_info.cpp

@@ -40,7 +40,7 @@ status_t ocl_gpu_device_info_t::init_arch(engine_t *engine) {
     OCL_CHECK(err);
 
     init_gpu_hw_info(engine, device, context, gpu_arch_, stepping_id_,
-            mayiuse_systolic_, mayiuse_ngen_kernels_);
+            mayiuse_systolic_, mayiuse_ngen_kernels_, is_xelpg_);
 
     err = clReleaseContext(context);
     OCL_CHECK(err);

src/gpu/ocl/ocl_gpu_hw_info.cpp

@@ -28,11 +28,13 @@ namespace ocl {
 
 void init_gpu_hw_info(engine_t *engine, cl_device_id device, cl_context context,
         compute::gpu_arch_t &gpu_arch, int &stepping_id, bool &mayiuse_systolic,
-        bool &mayiuse_ngen_kernels) {
+        bool &mayiuse_ngen_kernels, bool &is_xelpg) {
     using namespace ngen;
     HW hw = HW::Unknown;
     Product product = {ProductFamily::Unknown, 0};
     jit::jit_generator<HW::Unknown>::detectHWInfo(context, device, hw, product);
+    is_xelpg = (product.family == ngen::ProductFamily::ARL
+            || product.family == ngen::ProductFamily::MTL);
 
     gpu_arch = jit::convert_ngen_arch_to_dnnl(hw);
     stepping_id = product.stepping;

src/gpu/ocl/ocl_gpu_hw_info.hpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
-* Copyright 2020-2023 Intel Corporation
+* Copyright 2020-2024 Intel Corporation
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
@@ -29,7 +29,7 @@ namespace ocl {
 
 void init_gpu_hw_info(engine_t *engine, cl_device_id device, cl_context context,
         compute::gpu_arch_t &gpu_arch, int &stepping_id, bool &mayiuse_systolic,
-        bool &mayiuse_ngen_kernels);
+        bool &mayiuse_ngen_kernels, bool &is_xelpg);
 
 } // namespace ocl
 } // namespace gpu

src/sycl/sycl_device_info.cpp

@@ -52,7 +52,7 @@ status_t sycl_device_info_t::init_arch(engine_t *engine) {
 
         gpu::ocl::init_gpu_hw_info(engine, ocl_dev_wrapper, ocl_ctx_wrapper,
                 gpu_arch_, stepping_id_, mayiuse_systolic_,
-                mayiuse_ngen_kernels_);
+                mayiuse_ngen_kernels_, is_xelpg_);
     } else if (be == backend_t::level0) {
         // TODO: add support for L0 binary ngen check
         // XXX: query from ocl_engine for now
@@ -71,6 +71,7 @@ status_t sycl_device_info_t::init_arch(engine_t *engine) {
         stepping_id_ = dev_info->stepping_id();
         mayiuse_systolic_ = dev_info->mayiuse_systolic();
         mayiuse_ngen_kernels_ = dev_info->mayiuse_ngen_kernels();
+        is_xelpg_ = dev_info->is_xelpg();
     } else {
         assert(!"not_expected");
     }