RTL code for the DPU chip designed for irregular graph.
The top design module is in src/pru_async_top.sv
The top testbench module is in tb/testbench_top.sv
If you use this repository, please cite our related works:
[1] Nimish Shah, Laura Isabel Galindez Olascoaga, Shirui Zhao, Wannes Meert, and Marian Verhelst. "DPU: DAG Processing Unit for Irregular Graphs With Precision-Scalable Posit Arithmetic in 28 nm." IEEE Journal of Solid-State Circuits (2021).
[2] Nimish Shah, Laura Isabel Galindez Olascoaga, Shirui Zhao, Wannes Meert, and Marian Verhelst. "9.4 PIU: A 248GOPS/W Stream-Based Processor for Irregular Probabilistic Inference Networks Using Precision-Scalable Posit Arithmetic in 28nm." In 2021 IEEE International Solid-State Circuits Conference (ISSCC), vol. 64, pp. 150-152. IEEE, 2021.