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Add RV64 constraint to SRLIW #69416

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merged 5 commits into from
Oct 18, 2023
Merged

Add RV64 constraint to SRLIW #69416

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5908e29
Add RV64 constraint to SRLIW
Oct 18, 2023
e8c97bc
fixup! Revoke most erroneous operations
Oct 18, 2023
2203a9a
fixup!
Oct 18, 2023
3cdbd75
fixup! Merge duplicate code
Oct 18, 2023
6f550b7
fixup! Fix comment
Oct 18, 2023
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15 changes: 11 additions & 4 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1015,10 +1015,17 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
break;
// If the mask has 32 trailing ones, use SRLIW.
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if (TrailingOnes == 32) {
SDNode *SRLIW =
CurDAG->getMachineNode(RISCV::SRLIW, DL, VT, N0->getOperand(0),
CurDAG->getTargetConstant(ShAmt, DL, VT));
ReplaceNode(Node, SRLIW);
if (Subtarget->is64Bit()) {
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SDNode *SRLIW =
CurDAG->getMachineNode(RISCV::SRLIW, DL, VT, N0->getOperand(0),
CurDAG->getTargetConstant(ShAmt, DL, VT));
ReplaceNode(Node, SRLIW);
} else {
SDNode *SRLI =
CurDAG->getMachineNode(RISCV::SRLI, DL, VT, N0->getOperand(0),
CurDAG->getTargetConstant(ShAmt, DL, VT));
ReplaceNode(Node, SRLI);
}
return;
}

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21 changes: 21 additions & 0 deletions llvm/test/CodeGen/RISCV/aext.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,21 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s

define i24 @aext(i32 %0) {
; RV32I-LABEL: aext:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a0, a0, 8
; RV32I-NEXT: ret
;
; RV64I-LABEL: aext:
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a0, a0, 8
; RV64I-NEXT: ret
%2 = and i32 %0, -256
%3 = lshr exact i32 %2, 8
%4 = trunc i32 %3 to i24
ret i24 %4
}