Split protable vector types tests into multiple crates (rust-lang#379)

* split the portable vector tests into separate crates * use rustc reductions
danielverkamp · Mar 18, 2018 · c5cf3bc · c5cf3bc
1 parent 3a5ab60
commit c5cf3bc
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Showing 44 changed files with 1,039 additions and 1,756 deletions.
diff --git a/ci/run.sh b/ci/run.sh
@@ -2,21 +2,14 @@
 
 set -ex
 
+: ${TARGET?"The TARGET environment variable must be set."}
+
 # Tests are all super fast anyway, and they fault often enough on travis that
 # having only one thread increases debuggability to be worth it.
 export RUST_TEST_THREADS=1
 #export RUST_BACKTRACE=1
 #export RUST_TEST_NOCAPTURE=1
 
-# FIXME(rust-lang-nursery/stdsimd#120) run-time feature detection for ARM Neon
-case ${TARGET} in
-    aarch*)
-        export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+neon"
-        ;;
-    *)
-        ;;
-esac
-
 FEATURES="strict,$FEATURES"
 
 echo "RUSTFLAGS=${RUSTFLAGS}"
@@ -25,7 +18,8 @@ echo "OBJDUMP=${OBJDUMP}"
 
 cargo_test() {
     cmd="cargo test --target=$TARGET --features $FEATURES $1"
-    cmd="$cmd -p coresimd -p stdsimd --manifest-path crates/stdsimd/Cargo.toml"
+    cmd="$cmd -p coresimd -p stdsimd"
+    cmd="$cmd --manifest-path crates/stdsimd/Cargo.toml"
     cmd="$cmd -- $2"
     $cmd
 }

diff --git a/coresimd/ppsv/api/arithmetic_ops.rs b/coresimd/ppsv/api/arithmetic_ops.rs
@@ -1,76 +1,82 @@
 //! Lane-wise arithmetic operations.
+#![allow(unused)]
 
 macro_rules! impl_arithmetic_ops {
     ($id:ident) => {
-        impl ops::Add for $id {
+        impl ::ops::Add for $id {
             type Output = Self;
             #[inline]
             fn add(self, other: Self) -> Self {
+                use coresimd::simd_llvm::simd_add;
                 unsafe { simd_add(self, other) }
             }
         }
 
-        impl ops::Sub for $id {
+        impl ::ops::Sub for $id {
             type Output = Self;
             #[inline]
             fn sub(self, other: Self) -> Self {
+                use coresimd::simd_llvm::simd_sub;
                 unsafe { simd_sub(self, other) }
             }
         }
 
-        impl ops::Mul for $id {
+        impl ::ops::Mul for $id {
             type Output = Self;
             #[inline]
             fn mul(self, other: Self) -> Self {
+                use coresimd::simd_llvm::simd_mul;
                 unsafe { simd_mul(self, other) }
             }
         }
 
-        impl ops::Div for $id {
+        impl ::ops::Div for $id {
             type Output = Self;
             #[inline]
             fn div(self, other: Self) -> Self {
+                use coresimd::simd_llvm::simd_div;
                 unsafe { simd_div(self, other) }
             }
         }
 
-        impl ops::Rem for $id {
+        impl ::ops::Rem for $id {
             type Output = Self;
             #[inline]
             fn rem(self, other: Self) -> Self {
+                use coresimd::simd_llvm::simd_rem;
                 unsafe { simd_rem(self, other) }
             }
         }
 
-        impl ops::AddAssign for $id {
+        impl ::ops::AddAssign for $id {
             #[inline]
             fn add_assign(&mut self, other: Self) {
                 *self = *self + other;
             }
         }
 
-        impl ops::SubAssign for $id {
+        impl ::ops::SubAssign for $id {
             #[inline]
             fn sub_assign(&mut self, other: Self) {
                 *self = *self - other;
             }
         }
 
-        impl ops::MulAssign for $id {
+        impl ::ops::MulAssign for $id {
             #[inline]
             fn mul_assign(&mut self, other: Self) {
                 *self = *self * other;
             }
         }
 
-        impl ops::DivAssign for $id {
+        impl ::ops::DivAssign for $id {
             #[inline]
             fn div_assign(&mut self, other: Self) {
                 *self = *self / other;
             }
         }
 
-        impl ops::RemAssign for $id {
+        impl ::ops::RemAssign for $id {
             #[inline]
             fn rem_assign(&mut self, other: Self) {
                 *self = *self % other;
@@ -80,7 +86,6 @@ macro_rules! impl_arithmetic_ops {
 }
 
 #[cfg(test)]
-#[macro_export]
 macro_rules! test_arithmetic_ops {
     ($id:ident, $elem_ty:ident) => {
         #[test]

diff --git a/coresimd/ppsv/api/arithmetic_reductions.rs b/coresimd/ppsv/api/arithmetic_reductions.rs
@@ -1,17 +1,65 @@
 //! Implements portable arithmetic vector reductions.
+#![allow(unused)]
 
 macro_rules! impl_arithmetic_reductions {
     ($id:ident, $elem_ty:ident) => {
         impl $id {
             /// Lane-wise addition of the vector elements.
+            ///
+            /// FIXME: document guarantees with respect to:
+            ///    * integers: overflow behavior
+            ///    * floats: order and NaNs
+            #[cfg(not(target_arch = "aarch64"))]
             #[inline]
             pub fn sum(self) -> $elem_ty {
-                ReduceAdd::reduce_add(self)
+                use ::coresimd::simd_llvm::simd_reduce_add_ordered;
+                unsafe {
+                    simd_reduce_add_ordered(self, 0 as $elem_ty)
+                }
             }
+            /// Lane-wise addition of the vector elements.
+            ///
+            /// FIXME: document guarantees with respect to:
+            ///    * integers: overflow behavior
+            ///    * floats: order and NaNs
+            #[cfg(target_arch = "aarch64")]
+            #[inline]
+            pub fn sum(self) -> $elem_ty {
+                // FIXME: broken on AArch64
+                let mut x = self.extract(0) as $elem_ty;
+                for i in 1..$id::lanes() {
+                    x += self.extract(i) as $elem_ty;
+                }
+                x
+            }
+
             /// Lane-wise multiplication of the vector elements.
+            ///
+            /// FIXME: document guarantees with respect to:
+            ///    * integers: overflow behavior
+            ///    * floats: order and NaNs
+            #[cfg(not(target_arch = "aarch64"))]
             #[inline]
             pub fn product(self) -> $elem_ty {
-                ReduceMul::reduce_mul(self)
+                use ::coresimd::simd_llvm::simd_reduce_mul_ordered;
+                unsafe {
+                    simd_reduce_mul_ordered(self, 1 as $elem_ty)
+                }
+            }
+            /// Lane-wise multiplication of the vector elements.
+            ///
+            /// FIXME: document guarantees with respect to:
+            ///    * integers: overflow behavior
+            ///    * floats: order and NaNs
+            #[cfg(target_arch = "aarch64")]
+            #[inline]
+            pub fn product(self) -> $elem_ty {
+                // FIXME: broken on AArch64
+                let mut x = self.extract(0) as $elem_ty;
+                for i in 1..$id::lanes() {
+                    x *= self.extract(i) as $elem_ty;
+                }
+                x
             }
         }
     }

diff --git a/coresimd/ppsv/api/bitwise_ops.rs b/coresimd/ppsv/api/bitwise_ops.rs
@@ -1,48 +1,52 @@
 //! Lane-wise bitwise operations for integer and boolean vectors.
+#![allow(unused)]
 
 macro_rules! impl_bitwise_ops {
     ($ty:ident, $true_val:expr) => {
-        impl ops::Not for $ty {
+        impl ::ops::Not for $ty {
             type Output = Self;
             #[inline]
             fn not(self) -> Self {
                 Self::splat($true_val) ^ self
             }
         }
-        impl ops::BitXor for $ty {
+        impl ::ops::BitXor for $ty {
             type Output = Self;
             #[inline]
             fn bitxor(self, other: Self) -> Self {
+                use coresimd::simd_llvm::simd_xor;
                 unsafe { simd_xor(self, other) }
             }
         }
-        impl ops::BitAnd for $ty {
+        impl ::ops::BitAnd for $ty {
             type Output = Self;
             #[inline]
             fn bitand(self, other: Self) -> Self {
+                use coresimd::simd_llvm::simd_and;
                 unsafe { simd_and(self, other) }
             }
         }
-        impl ops::BitOr for $ty {
+        impl ::ops::BitOr for $ty {
             type Output = Self;
             #[inline]
             fn bitor(self, other: Self) -> Self {
+                use coresimd::simd_llvm::simd_or;
                 unsafe { simd_or(self, other) }
             }
         }
-        impl ops::BitAndAssign for $ty {
+        impl ::ops::BitAndAssign for $ty {
             #[inline]
             fn bitand_assign(&mut self, other: Self) {
                 *self = *self & other;
             }
         }
-        impl ops::BitOrAssign for $ty {
+        impl ::ops::BitOrAssign for $ty {
             #[inline]
             fn bitor_assign(&mut self, other: Self) {
                 *self = *self | other;
             }
         }
-        impl ops::BitXorAssign for $ty {
+        impl ::ops::BitXorAssign for $ty {
             #[inline]
             fn bitxor_assign(&mut self, other: Self) {
                 *self = *self ^ other;
@@ -52,7 +56,6 @@ macro_rules! impl_bitwise_ops {
 }
 
 #[cfg(test)]
-#[macro_export]
 macro_rules! test_int_bitwise_ops {
     ($id:ident, $elem_ty:ident) => {
         #[test]
@@ -117,7 +120,6 @@ macro_rules! test_int_bitwise_ops {
 }
 
 #[cfg(test)]
-#[macro_export]
 macro_rules! test_bool_bitwise_ops {
     ($id:ident) => {
         #[test]