malta uhci quirks: make allowance for slow 4k(e)c

This works around an unexpected IRQ torvalds#255 seen during initial USB host mass storage device initialization and access. * wait up to 50us for HCRESET to clear, a slow 4kc needs a longer time. * leave FSBR enabled so that a slow 4kec/24kec will not be overwhelmed. Signed-off-by: <[email protected]> Weixing Shi Signed-off-by: <[email protected]> Bruce Ashfield
cythe · Dec 28, 2020 · 5108504 · 5108504
1 parent 8246a44
commit 5108504
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Showing 2 changed files with 15 additions and 3 deletions.
diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c
@@ -639,6 +639,9 @@ EXPORT_SYMBOL_GPL(usb_amd_pt_check_port);
  */
 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
 {
+#ifdef CONFIG_MIPS_MALTA
+	int timeout = 10;
+#endif
 	/* Turn off PIRQ enable and SMI enable.  (This also turns off the
 	 * BIOS's USB Legacy Support.)  Turn off all the R/WC bits too.
 	 */
@@ -652,9 +655,16 @@ void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
 	outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
 	mb();
 	udelay(5);
-	if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
-		dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
 
+#ifdef CONFIG_MIPS_MALTA
+	while (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET) {
+	        if (--timeout < 0) {
+			dev_warn(&pdev->dev, "HCRESET timed out!\n");
+			break;
+		}
+		udelay(5);
+	}
+#endif
 	/* Just to be safe, disable interrupt requests and
 	 * make sure the controller is stopped.
 	 */

diff --git a/drivers/usb/host/uhci-q.c b/drivers/usb/host/uhci-q.c
@@ -72,7 +72,9 @@ static void uhci_fsbr_off(struct uhci_hcd *uhci)
 static void uhci_add_fsbr(struct uhci_hcd *uhci, struct urb *urb)
 {
 	struct urb_priv *urbp = urb->hcpriv;
-
+#ifdef CONFIG_MIPS_MALTA
+       return;
+#endif
 	urbp->fsbr = 1;
 }