Differences in performance of the lhu command on Rocket and spike

[90ICEDA]

Type of issue: bug report
Impact: unknown
Development Phase: proposal
Other information：

Hi, I noticed a difference between Rocket and spike implementations, when executing the lhu x8,-7(x21) instruction, spike will execute normally while Rocket will report an error about not being aligned, is this a stricter measure taken by Rocket in handling alignment errors?
I hope to get your reply, please correct me if my thinking is wrong, thanks!

[caizixian]

Per the spec

Regardless of EEI, loads and stores whose effective addresses are naturally aligned shall not raise an
address-misaligned exception. Loads and stores whose effective address is not naturally aligned to the
referenced datatype (i.e., the effective address is not divisible by the size of the access in bytes) have
behavior dependent on the EEI.

So unaligned access can fault, and it does in Rocket Chip. See

rocket-chip/src/main/scala/rocket/TLB.scala

Line 550 in 2fe6bb5

val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1.U)).orR