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Submodule linux 40c2158..f457f60: > iio: adc: ad9361: Avoid clobbering MGC set gain when switching gain tables > staging: iio: ad5933: switch buffer mode to software > ad9361: ad9361_dig_interface_timing_analysis(): Properly setup and cleanup > iio: ad9361: Highlight selected delay in interface tuning diagnostics > iio: ad9361: Rework digital tune function for readability and correctness > iio: ad9361: Consolidate PN checker status checks > iio: ad9361: Add a helper function to get the number of PHY channels > iio: ad9361: Reduce number of ALERT<->FDD transitions during interface tuning > iio: ad9361: Make sure to go to ALERT state when feedback clock changes > iio: ad9361: Fix tuning diagnostics output > iio: adc: ad9361: Return ERROR code when writing manual gain in AGC modes > iio: adc: ad9361: Fix erroneous clearing of the TO_ALERT bit > dts: zynqmp-zcu102-revB-ad9361-fmcomms*.dts: Fix/update clock usage > Merge branch '2017_R1' into xcomm_zynq > iio: frequency: adf5355: Fix ADF4355 AUX RF OUTPUT POWER setting > Merge pull request #29 from analogdevicesinc/ad9680_minor_fixes Submodule buildroot c9924ef..72f3cd7: > package: libad9361-iio: Add AD9361 library > package: libiio: Bump to Version 0.14 > configs/zynq_[pluto|m2k]_defconfig: use compiler searched in $PATH > M2k: Implement mechanism to store and retrieve calibration data > board/pluto/update.sh: MTD layout allow 64k and 4k erase blocks > board/m2k/msd/img/index_fr|es.html: Fix download link > board/m2k/msd/index.html: Fix English and German HTML landing pages Submodule hdl ba24909..bf3ba44: > fmcomms11: Update the SPI IO definitions > fmcomms11: Update the clock tree > fmcomms11: Delete trailing whitespaces > axi_dmac: Include TLAST in AXIS slave port > axi_dmac: Add limited TLAST support for streaming AXI source interface > axi_ad9361: xilinx LVDS interface: Restore previous feedback clock polarity > ad9434: Specified DEVICE_TYPE parameter options > axi_ad9434.v Add description for parameter > axi_ad9434: Fix bad parameter definition > adrv9371: Increase FCLK2 to 200MHz to support max sampling rates > avl_dacfifo: Fix avl_address generation > avl_dacfifo: Control the avl_burstcount inside the FSM > avl_dacfifo: Fix the last address buffer control > avl_dacfifo: dma_last_beats is transfered to avalon clock domain, without conditioning > daq2: Data underflow of DAC FIFO is monitored by the device core > avl_dacfifo: End of burst is not always end of a transaction Signed-off-by: Michael Hennerich <[email protected]>
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