axi_*: Infer clock and reset signals of an IP

A clock sink must be connected to clock source, and a reset sink to reset source, otherwise the tool will throw a synthesis warning. By properly inferring all the reset and clock signals of an IP, we can get rid of unwanted warning messages. The following IPs tcl script was updated: - axi_ad9434 - axi_hdmi_tx - util_cpack - util_adxcvr - axi_ad6676 - axi_ad9625 - axi_ad9379 - axi_ad9265 - util_tdd_sync - util_rfifo - util_wfifo - axi_ad9361 - axi_ad9467 - util_upack - axi_dacfifo - axi_ad9152 - axi_ad9680 - util_clkdiv - axi_ad9122 - axi_ad9684 - axi_mc_speed - axi_mc_current_monitor - axi_mc_controller - util_gmii_to_rgmii - util_adxcvr - axi_ad9379 - axi_hdmi - library - axi_fmcadc5_sync - util_adcfifo - util_mfifo - axi_jesd204_rx - axi_jesd204_tx - axi_ad9361 - axi_adxcvr_ip
analogdevicesinc · Apr 11, 2018 · 74b922f · 74b922f
1 parent 3b34e8b
commit 74b922f
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Showing 38 changed files with 318 additions and 12 deletions.
diff --git a/library/axi_ad6676/axi_ad6676_ip.tcl b/library/axi_ad6676/axi_ad6676_ip.tcl
@@ -30,5 +30,9 @@ set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
 
+ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
diff --git a/library/axi_ad9122/axi_ad9122_ip.tcl b/library/axi_ad9122/axi_ad9122_ip.tcl
@@ -35,5 +35,11 @@ set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::curr
 set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
 
+ipx::infer_bus_interface dac_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface dac_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface dac_clk_out_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface dac_clk_out_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface dac_div_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
diff --git a/library/axi_ad9152/axi_ad9152_ip.tcl b/library/axi_ad9152/axi_ad9152_ip.tcl
@@ -31,5 +31,8 @@ set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_cor
 set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]]
 
+ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
diff --git a/library/axi_ad9265/axi_ad9265_ip.tcl b/library/axi_ad9265/axi_ad9265_ip.tcl
@@ -33,4 +33,10 @@ adi_ip_properties axi_ad9265
 set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
 
+ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface adc_clk_in_P xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
diff --git a/library/axi_ad9361/axi_ad9361_ip.tcl b/library/axi_ad9361/axi_ad9361_ip.tcl
@@ -87,5 +87,12 @@ set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
   -of_objects [ipx::get_bus_interfaces s_axi_aclk \
   -of_objects [ipx::current_core]]]
 
+ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface l_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+
+ipx::infer_bus_interface gps_pps_irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
diff --git a/library/axi_ad9379/axi_ad9379_ip.tcl b/library/axi_ad9379/axi_ad9379_ip.tcl
@@ -43,5 +43,9 @@ set_property driver_value 0 [ipx::get_ports *dac_tx_ready* -of_objects [ipx::cur
 set_property driver_value 0 [ipx::get_ports *adc_rx_valid* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *adc_rx_os_valid* -of_objects [ipx::current_core]]
 
+ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface adc_os_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
diff --git a/library/axi_ad9434/axi_ad9434_ip.tcl b/library/axi_ad9434/axi_ad9434_ip.tcl
@@ -32,5 +32,8 @@ adi_ip_properties axi_ad9434
 
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
 
+ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
diff --git a/library/axi_ad9467/axi_ad9467_ip.tcl b/library/axi_ad9467/axi_ad9467_ip.tcl
@@ -32,4 +32,9 @@ adi_ip_properties axi_ad9467
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
 
+ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface adc_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
diff --git a/library/axi_ad9625/axi_ad9625_ip.tcl b/library/axi_ad9625/axi_ad9625_ip.tcl
@@ -33,5 +33,10 @@ set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_cor
 set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
 
+ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
+ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
diff --git a/library/axi_ad9680/axi_ad9680_ip.tcl b/library/axi_ad9680/axi_ad9680_ip.tcl
@@ -30,5 +30,8 @@ set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
 
+ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
diff --git a/library/axi_ad9684/axi_ad9684_ip.tcl b/library/axi_ad9684/axi_ad9684_ip.tcl
@@ -34,4 +34,10 @@ adi_ip_properties axi_ad9684
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
 
+ipx::infer_bus_interface adc_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
diff --git a/library/axi_ad9963/axi_ad9963_ip.tcl b/library/axi_ad9963/axi_ad9963_ip.tcl
@@ -43,13 +43,17 @@ set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::curr
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
 
-ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \
-  -of_objects [ipx::current_core]]
-set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
-  -of_objects [ipx::get_bus_interfaces s_axi_aclk \
-  -of_objects [ipx::current_core]]]
-
 adi_set_ports_dependency "delay_clk" "ADC_IODELAY_ENABLE == 1" 0
 
+ipx::infer_bus_interface trx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
+ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+
+ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
diff --git a/library/axi_adc_decimate/axi_adc_decimate_ip.tcl b/library/axi_adc_decimate/axi_adc_decimate_ip.tcl
@@ -21,7 +21,8 @@ adi_ip_add_core_dependencies { \
   analog.com:user:util_cic:1.0 \
 }
 
-ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core]
+ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
 
 ipx::save_core [ipx::current_core]
 
diff --git a/library/axi_adc_trigger/axi_adc_trigger_ip.tcl b/library/axi_adc_trigger/axi_adc_trigger_ip.tcl
@@ -13,7 +13,7 @@ adi_ip_files axi_adc_trigger [list \
 
 adi_ip_properties axi_adc_trigger
 
-ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core]
+ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
 
 ipx::save_core [ipx::current_core]
 
diff --git a/library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl b/library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl
@@ -18,7 +18,8 @@ adi_ip_files axi_dac_interpolate [list \
 
 adi_ip_properties axi_dac_interpolate
 
-ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core]
+ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
 
 ipx::save_core [ipx::current_core]
 
diff --git a/library/axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl b/library/axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl
@@ -13,5 +13,11 @@ adi_ip_files axi_fmcadc5_sync [list \
   "axi_fmcadc5_sync.v" ]
 
 adi_ip_properties axi_fmcadc5_sync
+
+ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
+ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface delay_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
diff --git a/library/axi_hdmi_rx/axi_hdmi_rx_ip.tcl b/library/axi_hdmi_rx/axi_hdmi_rx_ip.tcl
@@ -28,5 +28,8 @@ adi_ip_files axi_hdmi_rx [list \
 
 adi_ip_properties axi_hdmi_rx
 
+ipx::infer_bus_interface hdmi_rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface hdmi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl b/library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl
@@ -29,5 +29,9 @@ adi_ip_files axi_hdmi_tx [list \
 
 adi_ip_properties axi_hdmi_tx
 
+ipx::infer_bus_interface hdmi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface hdmi_out_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface vdma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
diff --git a/library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl b/library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl
@@ -16,7 +16,8 @@ adi_ip_files axi_logic_analyzer [list \
 
 adi_ip_properties axi_logic_analyzer
 
-ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core]
+ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface clk_out xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
 
 ipx::save_core [ipx::current_core]
 
diff --git a/library/axi_mc_controller/axi_mc_controller_ip.tcl b/library/axi_mc_controller/axi_mc_controller_ip.tcl
@@ -22,6 +22,9 @@ adi_ip_files axi_mc_controller [list \
 
 adi_ip_properties axi_mc_controller
 
+ipx::infer_bus_interface ref_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface ctrl_data_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
 
diff --git a/library/axi_mc_current_monitor/axi_mc_current_monitor_ip.tcl b/library/axi_mc_current_monitor/axi_mc_current_monitor_ip.tcl
@@ -20,6 +20,10 @@ adi_ip_files axi_mc_current_monitor [list \
 
 adi_ip_properties axi_mc_current_monitor
 
+ipx::infer_bus_interface ref_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface adc_clk_i xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface adc_clk_o xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
 
diff --git a/library/axi_mc_speed/axi_mc_speed_ip.tcl b/library/axi_mc_speed/axi_mc_speed_ip.tcl
@@ -21,6 +21,8 @@ adi_ip_files axi_mc_speed [list \
 
 adi_ip_properties axi_mc_speed
 
+ipx::infer_bus_interface ref_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
 
diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl
@@ -114,6 +114,8 @@ adi_add_bus "rx_status" "slave" \
     { "core_status_lane_latency" "lane_latency" } \
   }
 
+ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core]
+
 adi_add_bus_clock "core_clk" "rx_status:rx_event:rx_ilas_config:rx_cfg" \
   "core_reset" "master"
 

diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl
@@ -119,6 +119,8 @@ adi_add_bus "tx_ctrl" "master" \
     { "core_ctrl_manual_sync_request" "manual_sync_request" } \
   }
 
+ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core]
+
 adi_add_bus_clock "core_clk" "tx_status:tx_event:tx_ilas_config:tx_cfg:tx_ctrl" \
   "core_reset" "master"
 

diff --git a/library/util_adcfifo/util_adcfifo_ip.tcl b/library/util_adcfifo/util_adcfifo_ip.tcl
@@ -12,6 +12,11 @@ adi_ip_files util_adcfifo [list \
 
 adi_ip_properties_lite util_adcfifo
 
+ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+
+ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
 
diff --git a/library/util_clkdiv/util_clkdiv_ip.tcl b/library/util_clkdiv/util_clkdiv_ip.tcl
@@ -25,4 +25,6 @@ set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters S
 adi_add_bus clk_out master "xilinx.com:signal:clock_rtl:1.0" "xilinx.com:signal:clock:1.0" \
   [list {"clk_out" "CLK"}]
 
+ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
diff --git a/library/util_cpack/util_cpack_ip.tcl b/library/util_cpack/util_cpack_ip.tcl
@@ -28,6 +28,10 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CH
   [ipx::get_ports *_7* -of_objects [ipx::current_core]]
 
 ipx::remove_all_bus_interface [ipx::current_core]
+
+ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
 
diff --git a/library/util_extract/util_extract_ip.tcl b/library/util_extract/util_extract_ip.tcl
@@ -9,7 +9,8 @@ adi_ip_files util_extract [list \
 
 adi_ip_properties_lite util_extract
 
-ipx::remove_all_bus_interface [ipx::current_core]
+ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
 
diff --git a/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl b/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl
@@ -18,4 +18,10 @@ ipx::infer_bus_interface {rgmii_td rgmii_tx_ctl rgmii_txc rgmii_rd rgmii_rx_ctl
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.IODELAY_CTRL')) = 1} \
   [ipx::get_ports idelayctrl_clk -of_objects [ipx::current_core]]
 
+ipx::infer_bus_interface clk_20m xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface clk_25m xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface clk_125m xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface idelayctrl_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
diff --git a/library/util_mfifo/util_mfifo_ip.tcl b/library/util_mfifo/util_mfifo_ip.tcl
@@ -28,6 +28,12 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CH
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \
   [ipx::get_ports *_7* -of_objects [ipx::current_core]]
 
+ipx::infer_bus_interface din_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface din_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+
+ipx::infer_bus_interface dout_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface dout_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
 
diff --git a/library/util_rfifo/util_rfifo_ip.tcl b/library/util_rfifo/util_rfifo_ip.tcl
@@ -32,6 +32,11 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CH
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \
   [ipx::get_ports *_7* -of_objects [ipx::current_core]]
 
+ipx::infer_bus_interface din_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface dout_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface din_rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface dout_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
 
diff --git a/library/util_tdd_sync/util_tdd_sync_ip.tcl b/library/util_tdd_sync/util_tdd_sync_ip.tcl
@@ -12,5 +12,8 @@ adi_ip_files util_tdd_sync [list \
 
 adi_ip_properties_lite util_tdd_sync
 
+ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
diff --git a/library/util_upack/util_upack_ip.tcl b/library/util_upack/util_upack_ip.tcl
@@ -31,6 +31,9 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CH
   [ipx::get_ports *_7* -of_objects [ipx::current_core]]
 
 ipx::remove_all_bus_interface [ipx::current_core]
+
+ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
 
diff --git a/library/util_var_fifo/util_var_fifo_ip.tcl b/library/util_var_fifo/util_var_fifo_ip.tcl
@@ -9,7 +9,9 @@ adi_ip_files util_var_fifo [list \
 
 adi_ip_properties_lite util_var_fifo
 
-ipx::remove_all_bus_interface [ipx::current_core]
+ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
 
diff --git a/library/util_wfifo/util_wfifo_ip.tcl b/library/util_wfifo/util_wfifo_ip.tcl
@@ -31,6 +31,11 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CH
 set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \
   [ipx::get_ports *_7* -of_objects [ipx::current_core]]
 
+ipx::infer_bus_interface din_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface din_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface dout_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface dout_rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
 
 
diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl b/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
@@ -59,6 +59,10 @@ for {set n 0} {$n < 16} {incr n} {
 
 }
 
+ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface up_pll_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+
 set_property value s_axi:m_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
   -of_objects [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]]]
 

diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl b/library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl
@@ -76,5 +76,10 @@ set_property range 4294967296 [ipx::get_address_spaces axi \
 set_property width 512 [ipx::get_address_spaces axi \
   -of_objects [ipx::current_core]]
 
+ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface dma_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]
Original file line number	Diff line number	Diff line change
Expand Up		@@ -21,6 +21,8 @@ adi_ip_files axi_mc_speed [list \

		adi_ip_properties axi_mc_speed

		ipx::infer_bus_interface ref_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]

		ipx::save_core [ipx::current_core]