ad_dds: Separated phase width from data width

library/common/ad_dds.v

@@ -41,7 +41,8 @@ module ad_dds #(
 
   parameter   DISABLE = 0,
   parameter   DDS_TYPE = 1,
-  parameter   CORDIC_DW = 14) (
+  parameter   CORDIC_DW = 16,
+  parameter   CORDIC_PHASE_DW = 16) (
 
   // interface
 
@@ -90,8 +91,9 @@ module ad_dds #(
        // dds-1
 
        ad_dds_1 #(
+         .DDS_TYPE(DDS_TYPE),
          .CORDIC_DW(CORDIC_DW),
-         .DDS_TYPE(DDS_TYPE))
+         .CORDIC_PHASE_DW(CORDIC_PHASE_DW))
        i_dds_1_0 (
          .clk (clk),
          .angle (dds_phase_0),
@@ -101,8 +103,9 @@ module ad_dds #(
        // dds-2
 
        ad_dds_1 #(
+         .DDS_TYPE(DDS_TYPE),
          .CORDIC_DW(CORDIC_DW),
-         .DDS_TYPE(DDS_TYPE))
+         .CORDIC_PHASE_DW(CORDIC_PHASE_DW))
        i_dds_1_1 (
          .clk (clk),
          .angle (dds_phase_1),

library/common/ad_dds_1.v

@@ -40,7 +40,8 @@ module ad_dds_1 #(
   // parameters
 
   parameter   DDS_TYPE = 1,
-  parameter   CORDIC_DW = 16) (
+  parameter   CORDIC_DW = 16,
+  parameter   CORDIC_PHASE_DW = 16) (
 
   // interface
 
@@ -69,22 +70,26 @@ module ad_dds_1 #(
     if (DDS_TYPE == DDS_CORDIC_TYPE) begin
 
       // the cordic module input angle width must be equal with it's width
-      wire    [CORDIC_DW:0] angle_s;
+      wire    [CORDIC_PHASE_DW:0] angle_s;
 
+      if (CORDIC_PHASE_DW >= 16) begin
+        assign angle_s = {angle,{CORDIC_PHASE_DW-15{1'b0}}};
+      end else begin
+        assign angle_s = {angle[15:16-CORDIC_PHASE_DW],1'b0};
+      end
       if (CORDIC_DW >= 16) begin
-        assign angle_s = {angle,zeros[CORDIC_DW-16:0]};
         assign sine16_s = sine_s[CORDIC_DW-1:CORDIC_DW-16];
       end else begin
-        assign angle_s = {angle[15:16-CORDIC_DW],1'b0};
         assign sine16_s = {sine_s,zeros[15-CORDIC_DW:0]};
       end
 
       ad_dds_sine_cordic #(
         .CORDIC_DW(CORDIC_DW),
+        .PHASE_DW(CORDIC_PHASE_DW),
         .DELAY_DW(1))
       i_dds_sine (
         .clk (clk),
-        .angle (angle_s[CORDIC_DW:1]),
+        .angle (angle_s[CORDIC_PHASE_DW:1]),
         .sine (sine_s),
         .cosine (),
         .ddata_in (1'b0),

library/common/ad_dds_cordic_pipe.v

@@ -40,7 +40,9 @@ module ad_dds_cordic_pipe#(
   // parameters
 
   // Range = N/A
-  parameter DW = 16,
+  parameter P_DW = 16,
+  // Range = N/A
+  parameter D_DW = 16,
   // Range = N/A
   parameter DELAY_DW = 1,
   // Range = 0-(DW - 1)
@@ -50,13 +52,13 @@ module ad_dds_cordic_pipe#(
 
                       input                          clk,
   (* keep = "TRUE" *) input                          dir,
-  (* keep = "TRUE" *) input             [    DW-1:0] dataa_x,
-  (* keep = "TRUE" *) input             [    DW-1:0] dataa_y,
-  (* keep = "TRUE" *) input             [    DW-1:0] dataa_z,
-  (* keep = "TRUE" *) input             [    DW-1:0] datab_z,
-  (* keep = "TRUE" *) output reg        [    DW-1:0] result_x,
-  (* keep = "TRUE" *) output reg        [    DW-1:0] result_y,
-  (* keep = "TRUE" *) output reg        [    DW-1:0] result_z,
+  (* keep = "TRUE" *) input             [  D_DW-1:0] dataa_x,
+  (* keep = "TRUE" *) input             [  D_DW-1:0] dataa_y,
+  (* keep = "TRUE" *) input             [  P_DW-1:0] dataa_z,
+  (* keep = "TRUE" *) input             [  P_DW-1:0] datab_z,
+  (* keep = "TRUE" *) output reg        [  D_DW-1:0] result_x,
+  (* keep = "TRUE" *) output reg        [  D_DW-1:0] result_y,
+  (* keep = "TRUE" *) output reg        [  P_DW-1:0] result_z,
                       input             [DELAY_DW:1] data_delay_in,
                       output            [DELAY_DW:1] data_delay_out);
 
@@ -66,21 +68,21 @@ module ad_dds_cordic_pipe#(
 
   // Wires Declarations
 
-  wire  [    DW-1:0]  sgn_shift_x;
-  wire  [    DW-1:0]  sgn_shift_y;
+  wire  [  D_DW-1:0]  sgn_shift_x;
+  wire  [  D_DW-1:0]  sgn_shift_y;
   wire                dir_inv = ~dir;
 
-  // Previous stage shift
+  // Sign shift
 
-  assign sgn_shift_x = {{SHIFT{dataa_x[DW-1]}}, dataa_x[DW-1:SHIFT]};
-  assign sgn_shift_y = {{SHIFT{dataa_y[DW-1]}}, dataa_y[DW-1:SHIFT]};
+  assign sgn_shift_x = {{SHIFT{dataa_x[D_DW-1]}}, dataa_x[D_DW-1:SHIFT]};
+  assign sgn_shift_y = {{SHIFT{dataa_y[D_DW-1]}}, dataa_y[D_DW-1:SHIFT]};
 
   // Stage rotation
 
   always @(posedge clk) begin
-    result_x <= dataa_x + ({DW{dir_inv}} ^ sgn_shift_y) + dir_inv;
-    result_y <= dataa_y + ({DW{dir}}     ^ sgn_shift_x) + dir;
-    result_z <= dataa_z + ({DW{dir_inv}} ^     datab_z) + dir_inv;
+    result_x <= dataa_x + ({D_DW{dir_inv}} ^ sgn_shift_y) + dir_inv;
+    result_y <= dataa_y + ({D_DW{dir}}     ^ sgn_shift_x) + dir;
+    result_z <= dataa_z + ({P_DW{dir_inv}} ^     datab_z) + dir_inv;
   end
 
   // Delay data (if used)