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Adaq8092 on ZedBoard LVDS output mode (#921)
* common/up_adc_common: Add adc_custom_control register * library/axi_adaq8092: Initial commit * projects/adaq8092_fmc: Initial commit for ZedBoard
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#################################################################################### | ||
## Copyright (c) 2018 - 2021 Analog Devices, Inc. | ||
### SPDX short identifier: BSD-1-Clause | ||
## Auto-generated, do not modify! | ||
#################################################################################### | ||
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LIBRARY_NAME := axi_adaq8092 | ||
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GENERIC_DEPS += ../common/ad_datafmt.v | ||
GENERIC_DEPS += ../common/ad_rst.v | ||
GENERIC_DEPS += ../common/up_adc_channel.v | ||
GENERIC_DEPS += ../common/up_adc_common.v | ||
GENERIC_DEPS += ../common/up_axi.v | ||
GENERIC_DEPS += ../common/up_clock_mon.v | ||
GENERIC_DEPS += ../common/up_delay_cntrl.v | ||
GENERIC_DEPS += ../common/up_xfer_cntrl.v | ||
GENERIC_DEPS += ../common/up_xfer_status.v | ||
GENERIC_DEPS += axi_adaq8092.v | ||
GENERIC_DEPS += axi_adaq8092_apb_decode.v | ||
GENERIC_DEPS += axi_adaq8092_channel.v | ||
GENERIC_DEPS += axi_adaq8092_if.v | ||
GENERIC_DEPS += axi_adaq8092_rand_decode.v | ||
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XILINX_DEPS += ../xilinx/common/ad_data_clk.v | ||
XILINX_DEPS += ../xilinx/common/ad_data_in.v | ||
XILINX_DEPS += ../xilinx/common/ad_dcfilter.v | ||
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc | ||
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc | ||
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc | ||
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc | ||
XILINX_DEPS += axi_adaq8092_ip.tcl | ||
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include ../scripts/library.mk |
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