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Adaq8092 on ZedBoard LVDS output mode (#921)
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* common/up_adc_common: Add adc_custom_control register

* library/axi_adaq8092: Initial commit

* projects/adaq8092_fmc: Initial commit for ZedBoard
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PopPaul2021 authored Apr 28, 2022
1 parent 97b9256 commit 619e804
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Showing 17 changed files with 1,570 additions and 2 deletions.
2 changes: 2 additions & 0 deletions library/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,7 @@ clean:
$(MAKE) -C axi_ad9739a clean
$(MAKE) -C axi_ad9783 clean
$(MAKE) -C axi_ad9963 clean
$(MAKE) -C axi_adaq8092 clean
$(MAKE) -C axi_adc_decimate clean
$(MAKE) -C axi_adc_trigger clean
$(MAKE) -C axi_adrv9001 clean
Expand Down Expand Up @@ -145,6 +146,7 @@ lib:
$(MAKE) -C axi_ad9739a
$(MAKE) -C axi_ad9783
$(MAKE) -C axi_ad9963
$(MAKE) -C axi_adaq8092
$(MAKE) -C axi_adc_decimate
$(MAKE) -C axi_adc_trigger
$(MAKE) -C axi_adrv9001
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33 changes: 33 additions & 0 deletions library/axi_adaq8092/Makefile
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@@ -0,0 +1,33 @@
####################################################################################
## Copyright (c) 2018 - 2021 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################

LIBRARY_NAME := axi_adaq8092

GENERIC_DEPS += ../common/ad_datafmt.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_delay_cntrl.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_adaq8092.v
GENERIC_DEPS += axi_adaq8092_apb_decode.v
GENERIC_DEPS += axi_adaq8092_channel.v
GENERIC_DEPS += axi_adaq8092_if.v
GENERIC_DEPS += axi_adaq8092_rand_decode.v

XILINX_DEPS += ../xilinx/common/ad_data_clk.v
XILINX_DEPS += ../xilinx/common/ad_data_in.v
XILINX_DEPS += ../xilinx/common/ad_dcfilter.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_adaq8092_ip.tcl

include ../scripts/library.mk
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