Support for allowing direct VEXTRACT to 20-bit registers

[abhinay-anubola]

• This update introduces a new generic combiner that simplifies the sequence sext(trunc x) directly to x when applicable.
• Added VExtract combiner that enables above generic combiner, thus we have 20-bit vextract.
• The MachineVerifier has been updated to allow G_AIE_SEXT_EXTRACT_VECTOR_ELT and G_AIE_ZEXT_EXTRACT_VECTOR_ELT to accept 20-bit outputs.
• Additionally, tests have been added and updated to reflect these functional changes.

[krishnamtibrewala]

Given that you mentioned there are no QoR gain, I would recommend you to re look at the instruction that consume S20 type reg.
Because for the optimization starts to trace back from an instruction that consumes S20 type which might not be captured in isNativeS20Consumer function.

[andcarminati]

nit: const everywhere:

 bool CombinerHelper::matchCombineSextTrunc(MachineInstr &MI, Register &Reg) {
   assert(MI.getOpcode() == TargetOpcode::G_SEXT && "Expected a G_SEXT");
-  Register DstReg = MI.getOperand(0).getReg();
-  Register SrcReg = MI.getOperand(1).getReg();
-  LLT DstTy = MRI.getType(DstReg);
+  const Register DstReg = MI.getOperand(0).getReg();
+  const Register SrcReg = MI.getOperand(1).getReg();
+  const LLT DstTy = MRI.getType(DstReg);
   if (mi_match(SrcReg, MRI,
                m_GTrunc(m_all_of(m_Reg(Reg), m_SpecificType(DstTy))))) {
-    unsigned DstSize = DstTy.getScalarSizeInBits();
-    unsigned SrcSize = MRI.getType(SrcReg).getScalarSizeInBits();
+    const unsigned DstSize = DstTy.getScalarSizeInBits();
+    const unsigned SrcSize = MRI.getType(SrcReg).getScalarSizeInBits();
     return KB->computeNumSignBits(Reg) >= (DstSize - SrcSize + 1);
   }
   return false;

[andcarminati]

Now we are safe ;-)

[andcarminati]

nit: GetOneUseWithOpcode

[andcarminati]

nit: we can use:

    if (GetOneUseWithOpcode(UseDstReg, ExtOpcode, 20)) {
      return true;
    }

Because there is no further use for auto Ext.

Or even:

bool AIE2PreLegalizerCombinerImpl::canCombineVExtractElt(
    Register DstReg, bool SignVal, unsigned SrcEltSize) const {
  // Returns the single non-debug use of a register with a specific opcode
  // and destination size.
  auto GetOneUseWithOpcode =
      [&](const Register Reg, const unsigned OpcodeToCheck,
          const unsigned DstSize) -> std::optional<MachineInstr *> {
    if (MRI.hasOneNonDBGUser(Reg)) {
      MachineInstr &Use = *MRI.use_nodbg_instructions(Reg).begin();
      if (Use.getOpcode() == OpcodeToCheck) {
        const LLT DstRegTy = MRI.getType(Use.getOperand(0).getReg());
        if (DstRegTy.getSizeInBits() == DstSize)
          return &Use;
      }
    }
    return std::nullopt;
  };

  auto Trunc = GetOneUseWithOpcode(DstReg, TargetOpcode::G_TRUNC, SrcEltSize);

  if (!Trunc)
    return false;

  const MachineInstr *TruncMI = *Trunc;
  const unsigned ExtOpcode =
      SignVal ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
  const Register UseDstReg = TruncMI->getOperand(0).getReg();

  return GetOneUseWithOpcode(UseDstReg, ExtOpcode, 20).has_value();
}