[AIEX] Trim unnecessary empty bundles in TopInsert

Xilinx · Dec 11, 2024 · cc37cc3 · cc37cc3
1 parent 4a4f73d
commit cc37cc3
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Showing 6 changed files with 12 additions and 12 deletions.
diff --git a/llvm/lib/Target/AIE/AIEInterBlockScheduling.cpp b/llvm/lib/Target/AIE/AIEInterBlockScheduling.cpp
@@ -830,6 +830,13 @@ void InterBlockScheduling::emitInterBlockTop(BlockState &BS) {
   if (LBS.isPipelined()) {
     auto *DedicatedExit = makeDedicatedLoopExit(Loop, BB);
     if (DedicatedExit == BB) {
+
+      // Trim excedent empty bundles.
+      while (BS.TopInsert.back().empty()) {
+        assert(BS.TopInsert.back().getMetaInstrs().empty());
+        BS.TopInsert.pop_back();
+      }
+
       // If we are in the same BB, just emit.
       emitBundles(BS.TopInsert, DedicatedExit, DedicatedExit->begin(),
                   /*Move=*/false, /*EmitNops=*/false);

diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/bitwisexor.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/bitwisexor.mir
@@ -51,7 +51,7 @@
   ; CHECK-NEXT:  .L_LEnd0:
   ; CHECK-NEXT:    nopb ; nopa ; vst wh6, [p2, #32]; nopx ; vbneg_ltz.s8 x3, r25:r24, x1; nopv
   ; CHECK-NEXT:  // %bb.3: // %for.cond.cleanup
-  ; CHECK-NEXT:    vst wl6, [p2], #64; nopx ; vband x4, x0, x3
+  ; CHECK-NEXT:    nopb ; nopa ; vst wl6, [p2], #64; nopx ; vband x4, x0, x3; nopv
   ; CHECK-NEXT:    vband x5, x1, x2
   ; CHECK-NEXT:    vbor x6, x4, x5
   ; CHECK-NEXT:    vbneg_ltz.s8 x2, r25:r24, x0
@@ -63,9 +63,6 @@
   ; CHECK-NEXT:    vst wh6, [p2, #32]
   ; CHECK-NEXT:    vst wl6, [p2], #64
   ; CHECK-NEXT:    nop
-  ; CHECK-NEXT:    nop
-  ; CHECK-NEXT:    nop
-  ; CHECK-NEXT:    nop
   ; CHECK-NEXT:    .p2align 4
   ; CHECK-NEXT:  .LBB0_4: // %for.cond.cleanup
   ; CHECK-NEXT:    nopa ; ret lr

diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/large-II.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/large-II.mir
@@ -51,15 +51,14 @@
   ; CHECK-NEXT:  .L_LEnd0:
   ; CHECK-NEXT:    nopb ; lda r7, [p0], #4; st r0, [p1], #4; nopxm ; nopv
   ; CHECK-NEXT:  // %bb.3: // %for.cond.cleanup
-  ; CHECK-NEXT:    st r1, [p1], #4
+  ; CHECK-NEXT:    st r1, [p1], #4; nopx
   ; CHECK-NEXT:    st r2, [p1], #4
   ; CHECK-NEXT:    st r3, [p1], #4
   ; CHECK-NEXT:    st r4, [p1], #4
   ; CHECK-NEXT:    st r5, [p1], #4
   ; CHECK-NEXT:    st r6, [p1], #4
   ; CHECK-NEXT:    st r7, [p1], #4
   ; CHECK-NEXT:    nop
-  ; CHECK-NEXT:    nop
   ; CHECK-NEXT:    .p2align 4
   ; CHECK-NEXT:  .LBB0_4: // %for.cond.cleanup
   ; CHECK-NEXT:    nopa ; ret lr

diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/load-add-store.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/load-add-store.mir
@@ -42,15 +42,14 @@
   ; CHECK-NEXT:  .L_LEnd0:
   ; CHECK-NEXT:    nopb ; nopa ; nops ; add r0, r0, #1; nopm ; nopv
   ; CHECK-NEXT:  // %bb.3: // %for.cond.cleanup
-  ; CHECK-NEXT:    st r0, [p0], #4
+  ; CHECK-NEXT:    st r0, [p0], #4; nopx
   ; CHECK-NEXT:    add r0, r0, #1
   ; CHECK-NEXT:    st r0, [p0], #4
   ; CHECK-NEXT:    add r0, r0, #1
   ; CHECK-NEXT:    st r0, [p0], #4
   ; CHECK-NEXT:    add r0, r0, #1
   ; CHECK-NEXT:    st r0, [p0], #4
   ; CHECK-NEXT:    nop
-  ; CHECK-NEXT:    nop
   ; CHECK-NEXT:    .p2align 4
   ; CHECK-NEXT:  .LBB0_4: // %for.cond.cleanup
   ; CHECK-NEXT:    nopa ; ret lr

diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/load-mac-store.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/load-mac-store.mir
@@ -42,15 +42,14 @@
   ; CHECK-NEXT:  .L_LEnd0:
   ; CHECK-NEXT:    nopb ; nopa ; nops ; add r0, r0, #1; nopm ; nopv
   ; CHECK-NEXT:  // %bb.3: // %for.cond.cleanup
-  ; CHECK-NEXT:    st r0, [p0], #4
+  ; CHECK-NEXT:    st r0, [p0], #4; nopx
   ; CHECK-NEXT:    add r0, r0, #1
   ; CHECK-NEXT:    st r0, [p0], #4
   ; CHECK-NEXT:    add r0, r0, #1
   ; CHECK-NEXT:    st r0, [p0], #4
   ; CHECK-NEXT:    add r0, r0, #1
   ; CHECK-NEXT:    st r0, [p0], #4
   ; CHECK-NEXT:    nop
-  ; CHECK-NEXT:    nop
   ; CHECK-NEXT:    .p2align 4
   ; CHECK-NEXT:  .LBB0_4: // %for.cond.cleanup
   ; CHECK-NEXT:    nopa ; ret lr

diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/small-II.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/small-II.mir
@@ -47,15 +47,14 @@
   ; CHECK-NEXT:  .L_LEnd0:
   ; CHECK-NEXT:    nopb ; lda r3, [p0], #4; st r0, [p1], #4; nopxm ; nopv
   ; CHECK-NEXT:  // %bb.3: // %for.cond.cleanup
-  ; CHECK-NEXT:    st r1, [p1], #4
+  ; CHECK-NEXT:    st r1, [p1], #4; nopx
   ; CHECK-NEXT:    st r2, [p1], #4
   ; CHECK-NEXT:    st r3, [p1], #4
   ; CHECK-NEXT:    st r0, [p1], #4
   ; CHECK-NEXT:    st r1, [p1], #4
   ; CHECK-NEXT:    st r2, [p1], #4
   ; CHECK-NEXT:    st r3, [p1], #4
   ; CHECK-NEXT:    nop
-  ; CHECK-NEXT:    nop
   ; CHECK-NEXT:    .p2align 4
   ; CHECK-NEXT:  .LBB0_4: // %for.cond.cleanup
   ; CHECK-NEXT:    nopa ; ret lr