Merge pull request #8 from hell03end/dev/python

First beta release

.gitattributes

@@ -0,0 +1,55 @@
+# Linux scripts
+# ============
+*.sh		text eol=lf
+
+# Source files
+# ============
+*.py 		text
+*.sql  		text
+*.vb  		text
+*.cs  		text
+*.json		text
+*.md		text
+*.rst		text
+*.xml		text
+*.txt		text
+*.v 		text
+*.qsf 		text
+*.qpf 		text
+*.bdf 		text
+*.bsf 		text
+*.qip 		text
+*.do 		text
+*.vwf		text
+*.emx		text
+*.tc		text
+*.linq		text
+*.erd		binary
+*.spl7		binary
+*.xlsx		binary
+*.accdb		binary
+*.docx      binary
+*.pptx      binary
+
+# Binary files
+# ============
+*.config	text
+*.db		binary
+*.resx		binary
+*.p 		binary
+*.pkl 		binary
+*.pyc 		binary
+*.pyd		binary
+*.pyo 		binary
+*.jpg       binary
+*.png       binary
+*.zip       binary
+*.rar       binary
+*.gz        binary
+*.pdf       binary
+*.doc       binary
+*.npy       binary
+*.pkz       binary
+*.model     binary
+
+*.ipynb linguist-language=Python

.gitignore

@@ -1,114 +1,41 @@
-etc/*
-
-### Quartus
-!etc/LabsQuartus
-etc/LabsQuartus/*
-!etc/LabsQuartus/Lab*
-etc/LabsQuartus/Lab*/*
-!etc/LabsQuartus/Lab*/*.bdf
-!etc/LabsQuartus/Lab*/*.vwf
-!etc/LabsQuartus/Lab*/*.qpf
-
-### Verilog (especially for SoC)
-!etc/LabsSoC
-etc/LabsSoC/*
-
-### General
-# Byte-compiled / optimized / DLL
-*.log*
-*.*data*
-*.dll
-*.o
-*.a
+# ===== Common =====
+__pycache__/
+.generated/
+.vscode/
+.cache/
+build/
+.idea/
+.venv/
+.env/
+temp/
+logs/
+log/
 
-# Media
-*.doc
-*.docx
-*.xml
-*.pdf
-*.png
-*.jpg
-*.jpeg
-*.html
+.env
+*tmp*
 
-# Resources:
-*.xml
-*.bak
-*.JSON
-logs
+*.py[cod]
 *.log
+*$py.class
+*.bak
 *.db
-*bootstrap*
-*npm*
-*glyphicons*
 
-# Specific PATHs:
-.vscode/
-.idea/
-db_repository/
-downloads/
+# ===== Altera Soft =====
+incremental_db/
+output_files/
+simulation/
+db/
+
+# ===== Web Client =====
 bak/
 rsc/
-tmp/
-bin/
 
-# Translations
-*.mo
+*.JSON
+*.db
+*.db.journal
 *.pot
+*.mo
 
-# Logs
-npm-debug.log*
-yarn-debug.log*
-yarn-error.log*
-
-# Runtime data
-pids
-*.pid
-*.seed
-*.pid.lock
-
-# Directory for instrumented libs generated by jscoverage/JSCover
-lib-cov
-
-# Coverage directory used by tools like istanbul
-coverage
-
-# nyc test coverage
-.nyc_output
-
-# Grunt intermediate storage (http://gruntjs.com/creating-plugins#storing-task-files)
-.grunt
-
-# Bower dependency directory (https://bower.io/)
-bower_components
-
-# node-waf configuration
-.lock-wscript
-
-# Compiled binary addons (http://nodejs.org/api/addons.html)
-build/Release
-
-# Dependency directories
-node_modules/
-jspm_packages/
-
-# Typescript v1 declaration files
-typings/
-
-# Optional npm cache directory
-.npm
-
-# Optional eslint cache
-.eslintcache
-
-# Optional REPL history
-.node_repl_history
-
-# Output of 'npm pack'
-*.tgz
-
-# Yarn Integrity file
-.yarn-integrity
-
-# dotenv environment variables file
-.env
+# Flask stuff:
+instance/
+.webassets-cache

README.md

@@ -1,8 +1,64 @@
-# FPGAMarsohodCAD
-[![Build Status](https://travis-ci.com/hell03end/FPGAMarsohodCAD.svg?token=eSmHFpkLmTo93ZHUMUtp&branch=master)](https://travis-ci.com/hell03end/FPGAMarsohodCAD)
-
+FPGAMarsohodCAD
+===============
 CAD for automatically configuring FPGA "Marsohod"
 
+#### Requirements
+* Python >= 3.6
+
+#### Examples
+See `engine_example.py` and `convert_example.py`.
+
+FPGA Marsohod CAD web interface
+-------------------------------
+#### How to run [linux]?
+```bash
+# first, clone repository
+git clone https://github.com/hell03end/FPGAMarsohodCAD
+
+# install dependencies
+pip install --no-cache -r requirements.txt
+pip install --no-cache -r engine/requirements.txt
+
+# set environment variables [use 'set' instead of 'export' for winfows]
+export FLASK_APP=run_web.py
+export STATIC_PATH=.generated # where to store generated configs
+
+# [use '%STATIC_PATH%' for windows]
+mkdir $STATIC_PATH
+
+# create database
+flask db upgrade
+
+# compile translations (optional)
+flask translate compile
+
+# finally, run application
+flask run --with-threads
+```
+
+You also need to create `.env` file to configure mailing.
+
+Example:
+```bash
+SECRET_KEY=<secret key>
+MAIL_SERVER=smtp.googlemail.com
+MAIL_PORT=587
+MAIL_USE_TLS=1
+MAIL_USERNAME="[email protected]"
+MAIL_PASSWORD=<password>
+```
+
+<!-- ```bash
+# To get text run:
+pybabel extract -F babel.cfg -k _l -o messages.pot .
+# To add a translation run:
+pybabel init -i messages.pot -d web_client/translations -l ru
+# To update existing translations run:
+pybabel update -i messages.pot -d web_client/translations
+# To compile translations run:
+pybabel compile -d web_client/translations
+``` -->
+
 Read more on **[wiki](https://github.com/hell03end/FPGAMarsohodCAD/wiki)**.
 
 [`CHANGELOG`](https://github.com/hell03end/FPGAMarsohodCAD/wiki/Changelog)

babel.cfg

@@ -0,0 +1,4 @@
+[python: web_client/**.py]
+[jinja2: web_client/templates/**.html]
+[jinja2: web_client/templates/**.jinja]
+extensions=jinja2.ext.autoescape,jinja2.ext.with_

convert_example.py

@@ -0,0 +1,19 @@
+import logging
+import os
+
+# suspend engine logs
+logging.basicConfig(level=logging.ERROR)
+
+from engine.boards import BOARDS
+from engine.utils import PATHS
+from engine.utils.prepare import Convertor
+
+
+if __name__ == "__main__":
+    FROM_FMT = "yml"
+    TO_FMT = "json"
+
+    # convert yml static content to json and save it in the same location
+    for board in BOARDS:
+        from_path = os.path.join(PATHS.STATIC, ".".join((board, FROM_FMT)))
+        Convertor.convert(from_path, TO_FMT)

docs/.gitignore

@@ -0,0 +1 @@
+books*

docs/README.md

@@ -0,0 +1,39 @@
+Project Documentation
+=====================
+> TODO: Add documentation here.
+
+
+Engine
+------
+Contains configuration files rendering methods.
+
+**Usage example** can be found in `engine_example.py`.
+
+
+Web client
+----------
+Contains project WEB interface.
+
+Includes:
+* `web_client` - main part
+* `migrations` - database migrations
+
+
+Tests
+-----
+Contains unit and functional tests for all parts of the project.
+
+
+Navigation
+----------
+
+### Folders
+* `drivers` - contains additional drivers for **Marsohod** boards for Altera Quartus II software
+* `misc` - contains miscellaneous *Verilog* files which should be improved and added to the project in future releases
+* `pin_assignments` - contains correct pin assignments for **Marsohod** and **De SoC** boards
+
+### Archives
+--------
+* `articles` - usefull articles connected with *FPGA* and **Marsohod** themes
+<!-- * `books` - usefull books connected with *FPGA* and **Marsohod** themes -->
+* `datasheets` - official datasheets for **Marsohod** and **De SoC** boards