Updating CVA6 for OpenPiton to support HEAD

Flist.ariane

@@ -20,24 +20,24 @@
 +incdir+common/local/util/
 +incdir+corev_apu/register_interface/include/
 
+core/include/config_pkg.sv
 core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
 core/include/riscv_pkg.sv
 corev_apu/riscv-dbg/src/dm_pkg.sv
-vendor/openhwgroup/cvfpu/src/fpnew_pkg.sv
+core/cvfpu/src/fpnew_pkg.sv
 core/include/ariane_pkg.sv
-core/include/acc_pkg.sv
 corev_apu/tb/ariane_soc_pkg.sv
 vendor/pulp-platform/axi/src/axi_pkg.sv
 corev_apu/tb/ariane_axi_pkg.sv
 core/include/wt_cache_pkg.sv
 corev_apu/tb/axi_intf.sv
-core/include/cvxif_pkg.sv
 vendor/pulp-platform/common_cells/src/cf_math_pkg.sv
 core/include/instr_tracer_pkg.sv
 core/cvxif_example/include/cvxif_instr_pkg.sv
 core/acc_dispatcher.sv
 corev_apu/rv_plic/rtl/rv_plic_reg_pkg.sv
 common/local/util/sram.sv
+common/local/util/sram_cache.sv
 vendor/pulp-platform/common_cells/src/deprecated/rrarbiter.sv
 vendor/pulp-platform/common_cells/src/deprecated/fifo_v1.sv
 vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv
@@ -62,6 +62,8 @@ core/cache_subsystem/axi_adapter.sv
 core/alu.sv
 core/fpu_wrap.sv
 corev_apu/src/ariane.sv
+core/include/build_config_pkg.sv
+core/cva6_rvfi_probes.sv
 core/cva6.sv
 core/branch_unit.sv
 core/compressed_decoder.sv
@@ -83,22 +85,20 @@ core/issue_stage.sv
 core/load_unit.sv
 core/load_store_unit.sv
 core/lsu_bypass.sv
-core/mmu_sv39/mmu.sv
-core/mmu_sv39x4/cva6_mmu_sv39x4.sv
+core/cva6_mmu/cva6_shared_tlb.sv
+core/cva6_mmu/cva6_mmu.sv
 core/mult.sv
 core/multiplier.sv
 core/serdiv.sv
 core/perf_counters.sv
-core/mmu_sv39/ptw.sv
-core/mmu_sv39x4/ptw_sv39x4.sv
+core/cva6_mmu/cva6_ptw.sv
 core/ariane_regfile_ff.sv
-core/re_name.sv
 core/scoreboard.sv
 core/store_buffer.sv
+core/cva6_fifo_v3.sv
 core/amo_buffer.sv
 core/store_unit.sv
-core/mmu_sv39/tlb.sv
-core/mmu_sv39x4/tlb_sv39x4.sv
+core/cva6_mmu/cva6_tlb.sv
 core/commit_stage.sv
 core/cache_subsystem/wt_dcache_ctrl.sv
 core/cache_subsystem/wt_dcache_mem.sv
@@ -112,7 +112,6 @@ core/cache_subsystem/wt_cache_subsystem.sv
 corev_apu/clint/clint.sv
 corev_apu/clint/axi_lite_interface.sv
 corev_apu/riscv-dbg/debug_rom/debug_rom.sv
-corev_apu/riscv-dbg/src/dm_pkg.sv
 corev_apu/riscv-dbg/src/dm_csrs.sv
 corev_apu/riscv-dbg/src/dm_mem.sv
 corev_apu/riscv-dbg/src/dm_top.sv
@@ -139,25 +138,25 @@ corev_apu/fpga/src/axi_slice/src/axi_r_buffer.sv
 corev_apu/fpga/src/axi_slice/src/axi_aw_buffer.sv
 corev_apu/register_interface/src/apb_to_reg.sv
 corev_apu/register_interface/src/reg_intf.sv
-vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
-vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
-vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv
-vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
-vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
-vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
-vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
-vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
-vendor/openhwgroup/cvfpu/src/fpnew_cast_multi.sv
-vendor/openhwgroup/cvfpu/src/fpnew_classifier.sv
-vendor/openhwgroup/cvfpu/src/fpnew_divsqrt_multi.sv
-vendor/openhwgroup/cvfpu/src/fpnew_fma_multi.sv
-vendor/openhwgroup/cvfpu/src/fpnew_fma.sv
-vendor/openhwgroup/cvfpu/src/fpnew_noncomp.sv
-vendor/openhwgroup/cvfpu/src/fpnew_opgroup_block.sv
-vendor/openhwgroup/cvfpu/src/fpnew_opgroup_fmt_slice.sv
-vendor/openhwgroup/cvfpu/src/fpnew_opgroup_multifmt_slice.sv
-vendor/openhwgroup/cvfpu/src/fpnew_rounding.sv
-vendor/openhwgroup/cvfpu/src/fpnew_top.sv
+core/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
+core/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
+core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv
+core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
+core/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
+core/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
+core/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
+core/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
+core/cvfpu/src/fpnew_cast_multi.sv
+core/cvfpu/src/fpnew_classifier.sv
+core/cvfpu/src/fpnew_divsqrt_multi.sv
+core/cvfpu/src/fpnew_fma_multi.sv
+core/cvfpu/src/fpnew_fma.sv
+core/cvfpu/src/fpnew_noncomp.sv
+core/cvfpu/src/fpnew_opgroup_block.sv
+core/cvfpu/src/fpnew_opgroup_fmt_slice.sv
+core/cvfpu/src/fpnew_opgroup_multifmt_slice.sv
+core/cvfpu/src/fpnew_rounding.sv
+core/cvfpu/src/fpnew_top.sv
 core/pmp/src/pmp.sv
 core/pmp/src/pmp_entry.sv
 common/local/util/instr_tracer.sv
@@ -166,3 +165,5 @@ core/cvxif_example/instr_decoder.sv
 vendor/pulp-platform/common_cells/src/counter.sv
 vendor/pulp-platform/common_cells/src/delta_counter.sv
 core/cvxif_fu.sv
+core/cvxif_issue_register_commit_if_driver.sv
+core/cvxif_compressed_if_driver.sv

core/cache_subsystem/wt_l15_adapter.sv

@@ -48,6 +48,7 @@
 //           https://parallel.princeton.edu/openpiton/docs/micro_arch.pdf
 //
 
+`include "wt_l15_types.svh"
 
 module wt_l15_adapter
   import ariane_pkg::*;
@@ -57,7 +58,9 @@ module wt_l15_adapter
     parameter type icache_req_t = logic,
     parameter type icache_rtrn_t = logic,
     parameter type dcache_req_t = logic,
-    parameter type dcache_rtrn_t = logic
+    parameter type dcache_rtrn_t = logic,
+    parameter type l15_req_t = `L15_REQ_T(CVA6Cfg),
+    parameter type l15_rtrn_t = `L15_RTRN_T(CVA6Cfg)
 ) (
     input logic clk_i,
     input logic rst_ni,
@@ -79,55 +82,10 @@ module wt_l15_adapter
     output dcache_rtrn_t dcache_rtrn_o,
 
     // L15
-    output l15_req_t  l15_req_o,
+    output l15_req_t l15_req_o,
     input  l15_rtrn_t l15_rtrn_i
 );
 
-  localparam type l15_req_t = struct packed {
-    logic l15_val;  // valid signal, asserted with request
-    logic l15_req_ack;  // ack for response
-    wt_cache_pkg::l15_reqtypes_t l15_rqtype;  // see below for encoding
-    logic l15_nc;  // non-cacheable bit
-    logic [2:0]                        l15_size;                  // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte)
-    logic [CVA6Cfg.MEM_TID_WIDTH-1:0] l15_threadid;  // currently 0 or 1
-    logic l15_prefetch;  // unused in openpiton
-    logic l15_invalidate_cacheline;  // unused by Ariane as L1 has no ECC at the moment
-    logic l15_blockstore;  // unused in openpiton
-    logic l15_blockinitstore;  // unused in openpiton
-    logic [CVA6Cfg.DCACHE_SET_ASSOC_WIDTH-1:0] l15_l1rplway;  // way to replace
-    logic [39:0] l15_address;  // physical address
-    logic [63:0] l15_data;  // word to write
-    logic [63:0] l15_data_next_entry;  // unused in Ariane (only used for CAS atomic requests)
-    logic [wt_cache_pkg::L15_TLB_CSM_WIDTH-1:0] l15_csm_data;  // unused in Ariane
-    logic [3:0] l15_amo_op;  // atomic operation type
-  };
-  localparam type l15_rtrn_t = struct packed {
-    logic l15_ack;  // ack for request struct
-    logic l15_header_ack;  // ack for request struct
-    logic l15_val;  // valid signal for return struct
-    wt_l15_adapter::l15_rtrntypes_t l15_returntype;  // see below for encoding
-    logic l15_l2miss;  // unused in Ariane
-    logic [1:0] l15_error;  // unused in openpiton
-    logic l15_noncacheable;  // non-cacheable bit
-    logic l15_atomic;  // asserted in load return and store ack packets of atomic tx
-    logic [CVA6Cfg.MEM_TID_WIDTH-1:0] l15_threadid;  // used as transaction ID
-    logic l15_prefetch;  // unused in openpiton
-    logic l15_f4b;  // 4byte instruction fill from I/O space (nc).
-    logic [63:0] l15_data_0;  // used for both caches
-    logic [63:0] l15_data_1;  // used for both caches
-    logic [63:0] l15_data_2;  // currently only used for I$
-    logic [63:0] l15_data_3;  // currently only used for I$
-    logic l15_inval_icache_all_way;  // invalidate all ways
-    logic l15_inval_dcache_all_way;  // unused in openpiton
-    logic [15:4] l15_inval_address_15_4;  // invalidate selected cacheline
-    logic l15_cross_invalidate;  // unused in openpiton
-    logic [CVA6Cfg.DCACHE_SET_ASSOC_WIDTH-1:0] l15_cross_invalidate_way;  // unused in openpiton
-    logic l15_inval_dcache_inval;  // invalidate selected cacheline and way
-    logic l15_inval_icache_inval;  // unused in openpiton
-    logic [CVA6Cfg.DCACHE_SET_ASSOC_WIDTH-1:0] l15_inval_way;  // way to invalidate
-    logic l15_blockinitstore;  // unused in openpiton
-  };
-
   // request path
   icache_req_t icache_data;
   logic icache_data_full, icache_data_empty;
@@ -341,7 +299,7 @@ module wt_l15_adapter
   end
 
   // openpiton is big endian
-  if (SwapEndianess) begin : gen_swap
+  if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_L15_BIG_ENDIAN) begin : gen_swap
     assign dcache_rtrn_o.data = {
       swendian64(rtrn_fifo_data.l15_data_1), swendian64(rtrn_fifo_data.l15_data_0)
     };

core/cva6.sv

@@ -1544,7 +1544,7 @@ module cva6
   logic [CVA6Cfg.NrCommitPorts-1:0] pc_pop, pc_empty;
 
   for (genvar i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin : gen_pc_fifo
-    fifo_v3 #(
+    cva6_fifo_v3 #(
         .DATA_WIDTH(64),
         .DEPTH(PC_QUEUE_DEPTH),
         .FPGA_EN(CVA6Cfg.FpgaEn)

core/include/ariane_pkg.sv

@@ -254,6 +254,7 @@ package ariane_pkg;
   localparam int unsigned ICACHE_SET_ASSOC = `CONFIG_L1I_ASSOCIATIVITY;
   localparam int unsigned ICACHE_INDEX_WIDTH = $clog2(`CONFIG_L1I_SIZE / ICACHE_SET_ASSOC);
   localparam int unsigned ICACHE_TAG_WIDTH = riscv::PLEN - ICACHE_INDEX_WIDTH;
+  localparam int unsigned AXI_USER_WIDTH = 64;
   localparam int unsigned ICACHE_USER_LINE_WIDTH = (AXI_USER_WIDTH == 1) ? 4 : 128;  // in bit
   // D$
   localparam int unsigned DCACHE_LINE_WIDTH = `CONFIG_L1D_CACHELINE_WIDTH;

core/include/wt_l15_types.svh

@@ -0,0 +1,50 @@
+`ifndef WT_L15_TYPES_SVH
+`define WT_L15_TYPES_SVH
+
+`define L15_REQ_T(CVA6Cfg) struct packed { \
+  logic l15_val;  // valid signal, asserted with request \
+  logic l15_req_ack;  // ack for response \
+  wt_cache_pkg::l15_reqtypes_t l15_rqtype;  // see below for encoding \
+  logic l15_nc;  // non-cacheable bit \
+  logic [2:0]                        l15_size;                  // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte) \
+  logic [CVA6Cfg.MEM_TID_WIDTH-1:0] l15_threadid;  // currently 0 or 1 \
+  logic l15_prefetch;  // unused in openpiton \
+  logic l15_invalidate_cacheline;  // unused by Ariane as L1 has no ECC at the moment \
+  logic l15_blockstore;  // unused in openpiton \
+  logic l15_blockinitstore;  // unused in openpiton \
+  logic [CVA6Cfg.DCACHE_SET_ASSOC_WIDTH-1:0] l15_l1rplway;  // way to replace \
+  logic [39:0] l15_address;  // physical address \
+  logic [63:0] l15_data;  // word to write \
+  logic [63:0] l15_data_next_entry;  // unused in Ariane (only used for CAS atomic requests) \
+  logic [wt_cache_pkg::L15_TLB_CSM_WIDTH-1:0] l15_csm_data;  // unused in Ariane \
+  logic [3:0] l15_amo_op;  // atomic operation type \
+}
+
+`define L15_RTRN_T(CVA6Cfg) struct packed { \
+  logic l15_ack;  // ack for request struct \
+  logic l15_header_ack;  // ack for request struct \
+  logic l15_val;  // valid signal for return struct \
+  wt_cache_pkg::l15_rtrntypes_t l15_returntype;  // see below for encoding \
+  logic l15_l2miss;  // unused in Ariane \
+  logic [1:0] l15_error;  // unused in openpiton \
+  logic l15_noncacheable;  // non-cacheable bit \
+  logic l15_atomic;  // asserted in load return and store ack packets of atomic tx \
+  logic [CVA6Cfg.MEM_TID_WIDTH-1:0] l15_threadid;  // used as transaction ID \
+  logic l15_prefetch;  // unused in openpiton \
+  logic l15_f4b;  // 4byte instruction fill from I/O space (nc). \
+  logic [63:0] l15_data_0;  // used for both caches \
+  logic [63:0] l15_data_1;  // used for both caches \
+  logic [63:0] l15_data_2;  // currently only used for I$ \
+  logic [63:0] l15_data_3;  // currently only used for I$ \
+  logic l15_inval_icache_all_way;  // invalidate all ways \
+  logic l15_inval_dcache_all_way;  // unused in openpiton \
+  logic [15:4] l15_inval_address_15_4;  // invalidate selected cacheline \
+  logic l15_cross_invalidate;  // unused in openpiton \
+  logic [CVA6Cfg.DCACHE_SET_ASSOC_WIDTH-1:0] l15_cross_invalidate_way;  // unused in openpiton \
+  logic l15_inval_dcache_inval;  // invalidate selected cacheline and way \
+  logic l15_inval_icache_inval;  // unused in openpiton \
+  logic [CVA6Cfg.DCACHE_SET_ASSOC_WIDTH-1:0] l15_inval_way;  // way to invalidate \
+  logic l15_blockinitstore;  // unused in openpiton \
+}
+
+`endif