This is part of the "FPGA accelerated tcpdump with eBPF" project. Refer to these two repositories for more information on the topic:
- main repository - main repostiory
- bpfcap_fpga - RTL code in SystemVerilog
This is part of the "FPGA accelerated tcpdump with eBPF" project. Refer to these two repositories for more information on the topic: