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Update README.md
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@AUDIY
AUDIY authored Dec 15, 2024
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Expand Up @@ -4,7 +4,7 @@ Verilog IP that AUDIY originally designed.
Code reviews are welcome!

## Notice: This repository is no longer maintained.
The author made a decision to shift HDL from Verilog to SystemVerilog.
The author made a decision to shift HDL from Verilog to SystemVerilog.
So it means that the author doesn't maintain and use modules in this repository.

When the author is ready to upload new system verilog IPs, this repository will be archived.
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