Merge pull request #1 from AUDIY/SDPRAM_SINGLECLK_v011

Add SDPRAM_SINGLECLK Rev. 0.11 Operation is verified.
AUDIY · Feb 28, 2024 · ec58200 · ec58200
2 parents 8532a1f + 6ae9e45
commit ec58200
Showing 1 changed file with 8 additions and 8 deletions.
diff --git a/01_Memory/01_SDPRAM_SINGLECLK/SDPRAM_SINGLECLK.v b/01_Memory/01_SDPRAM_SINGLECLK/SDPRAM_SINGLECLK.v
@@ -3,9 +3,9 @@
 *
 * Simple Dual-Port RAM (Single Clock)
 *
-* Version: 0.10
+* Version: 0.11
 * Author : AUDIY
-* Date   : 2023/12/10
+* Date   : 2024/2/22
 *
 * Port
 *   Input
@@ -27,7 +27,7 @@
 *
 * License under CERN-OHL-P v2
 --------------------------------------------------------------------------------
-| Copyright AUDIY 2023.                                                        |
+| Copyright AUDIY 2023 - 2024.                                                 |
 |                                                                              |
 | This source describes Open Hardware and is licensed under the CERN-OHL-P v2. |
 |                                                                              |
@@ -62,7 +62,7 @@ module SDPRAM_SINGLECLK #(
 
     /* Local Parameters */
     localparam MEMORY_DEPTH = 2**ADDR_WIDTH;
-    localparam MAX_DATA     = (1 << ADDR_WIDTH) - 1;
+    //localparam MAX_DATA     = (1 << ADDR_WIDTH) - 1; // Unused now.
 
     /* Internal Wire/Register Definition */
     reg [DATA_WIDTH-1:0] RAM[MEMORY_DEPTH-1:0];
@@ -93,10 +93,10 @@ module SDPRAM_SINGLECLK #(
 
     /* Output */
     generate
-	if (OUTPUT_REG == "TRUE") begin
-	    assign RDATA_O = RDATA_REG_2P;
-        end else begin
-	    assign RDATA_O = RDATA_REG_1P;
+        if (OUTPUT_REG == "TRUE") begin : gen_reg2p
+            assign RDATA_O = RDATA_REG_2P;
+        end else begin : gen_reg1p
+            assign RDATA_O = RDATA_REG_1P;
         end
     endgenerate